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? 1997-2013 microchip technology inc. preliminary ds30453e-page 1 pic16c5x devices included in this data sheet: ?pic16c54 ? pic16cr54 ?pic16c55 ?pic16c56 ? pic16cr56 ?pic16c57 ? pic16cr57 ?pic16c58 ? pic16cr58 high-performance risc cpu: ? only 33 single word instructions to learn ? all instructions are single cycle except for pro- gram branches which are two-cycle ? operating speed: dc - 40 mhz clock input dc - 100 ns instruction cycle ? 12-bit wide instructions ? 8-bit wide data path ? seven or eight special function hardware registers ? two-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions peripheral features: ? 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler ? power-on reset (por) ? device reset timer (drt) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power saving sleep mode ? selectable oscillator options: - rc: low cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal cmos technology: ? low power, high speed cmos eprom/rom tech- nology ? fully static design ? wide operating voltage and temperature range: - eprom commercial/industrial 2.0v to 6.25v - rom commercial/industrial 2.0v to 6.25v - eprom extended 2.5v to 6.0v - rom extended 2.5v to 6.0v ? low power consumption - < 2 ma typical @ 5v, 4 mhz -15 ? a typical @ 3v, 32 khz - < 0.6 ? a typical standby current (with wdt disabled) @ 3v, 0 ? c to 70 ? c note: pic16c5x refers to all revisions of the part (i.e., pic16c54 refers to pic16c54, pic16c54a, and pic16c54c), unless specifically called out otherwise. device pins i/o eprom/ rom ram pic16c54 18 12 512 25 pic16c54a 18 12 512 25 pic16c54c 18 12 512 25 pic16cr54a 18 12 512 25 pic16cr54c 18 12 512 25 pic16c55 28 20 512 24 pic16c55a 28 20 512 24 pic16c56 18 12 1k 25 pic16c56a 18 12 1k 25 pic16cr56a 18 12 1k 25 pic16c57 28 20 2k 72 pic16c57c 28 20 2k 72 pic16cr57c 28 20 2k 72 pic16c58b 18 12 2k 73 pic16cr58b 18 12 2k 73 note: in this document, figure and table titles refer to all varieties of the part number indi- cated, (i.e., the title ?figure 15-1: load conditions for device timing specifica- tions - pic16c54a?, also refers to pic16lc54a and pic16lv54a parts), unless specifically called out otherwise. eprom/rom-based 8-bit cmos microcontroller series
pic16c5x ds30453e-page 2 preliminary ? 1997-2013 microchip technology inc. pin diagrams device differences note 1: if you change from this device to another device, please verify oscillator characteristics in your application. device voltage range oscillator selection (program) oscillator process technology (microns) rom equivalent mclr filter pic16c54 2.5-6.25 factory see note 1 1.2 pic16cr54a no pic16c54a 2.0-6.25 user see note 1 0.9 ? no pic16c54c 2.5-5.5 user see note 1 0.7 pic16cr54c yes pic16c55 2.5-6.25 factory see note 1 1.7 ? no pic16c55a 2.5-5.5 user see note 1 0.7 ? yes pic16c56 2.5-6.25 factory see note 1 1.7 ? no pic16c56a 2.5-5.5 user see note 1 0.7 pic16cr56a yes pic16c57 2.5-6.25 factory see note 1 1.2 ? no pic16c57c 2.5-5.5 user see note 1 0.7 pic16cr57c yes pic16c58b 2.5-5.5 user see note 1 0.7 pic16cr58b yes pic16cr54a 2.5-6.25 factory see note 1 1.2 n/a yes pic16cr54c 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr56a 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr57c 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr58b 2.5-5.5 factory see note 1 0.7 n/a yes pdip, soic, windowed cerdip pic16cr54 pic16c58 pic16cr58 pic16c54 ra1 ra0 osc1/clkin osc2/clkout v dd v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ssop pic16c56 pic16cr56 pic16cr54 pic16c58 pic16cr58 pic16c54 pic16c56 pic16cr56 ra2 ra3 t0cki mclr /v pp v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 pdip, soic, windowed cerdip pic16c57 pic16c55 mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 t0cki v dd v ss ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ssop pic16c55 v dd v ss pic16cr57 pic16cr57 t0cki v dd n/c v ss n/c ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 pic16c57 note: the table shown above shows the generic names of the pic16c5x devices. for device varieties, please refer to section 2.0.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 3 pic16c5x table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic16c5x device varieties ................................................................................................... ...................................................... 7 3.0 architectural overview ..................................................................................................... ........................................................... 9 4.0 oscillator configurations ..................................... .............................................................. ......................................................... 15 5.0 reset ....................................................................................................................... ................................................................... 19 6.0 memory organization ......................................................................................................... ........................................................ 25 7.0 i/o ports ................................................................................................................... .................................................................. 35 8.0 timer0 module and tmr0 register ............................................................................................. .............................................. 37 9.0 special features of the cpu................................................................................................. ..................................................... 43 10.0 instruction set summary .................................................................................................... ........................................................ 49 11.0 development support........................................................................................................ ......................................................... 61 12.0 electrical characteristics - pic16c54/55/56/57 ............................................................................. ............................................ 67 13.0 electrical characteristics - pic16cr54a .................................................................................... ............................................... 79 14.0 device characterization - pic16c54/55/56/57/cr54a.......................................................................... .................................... 91 15.0 electrical characteristics - pic16c54a..................................................................................... ............................................... 103 16.0 device characterization - pic16c54a ........................................................................................ ............................................. 117 17.0 electrical characteristics - pic16c54c/c r54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b ........................................ 131 18.0 device characterization - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b .......................................... 14 5 19.0 electrical characteristics - pic16c54c/c55a/c56a/c57c/c58b 40mhz ........................................................... .................... 155 20.0 device characterization - pic16c54c/c55a/c56a/c57c/c58b 40mhz .............................................................. .................. 165 21.0 packaging information...................................................................................................... ........................................................ 171 appendix a: compatibility ...................................................................................................... ....................................................... 182 on-line support................................................................................................................ ................................................................. 187 reader response ................................................................................................................ .............................................................. 188 product identification system .................................................................................................. .......................................................... 189 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic16c5x ds30453e-page 4 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 5 pic16c5x 1.0 general description the pic16c5x from microchip technology is a family of low cost, high performance, 8-bit fully static, eprom/rom-based cmos microcontrollers. it employs a risc architecture with only 33 single word/ single cycle instructions. all instructions are single cycle except for program branches which take two cycles. the pic16c5x delivers performance in an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time significantly. the pic16c5x products are equipped with special fea- tures that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscillator configurations to choose from, including the power saving lp (low power) oscillator and cost saving rc oscillator. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the uv erasable cerdip packaged versions are ideal for code development, while the cost effective one time programmable (otp) versions are suitable for production in any volume. the customer can take full advantage of microchip?s price leadership in otp microcontrollers, while benefiting from the otp?s flexibility. the pic16c5x products are supported by a full fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a low cost development programmer and a full featured programmer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic16c5x series fits perfectly in applications rang- ing from high speed automotive and appliance motor control to low power remote transmitters/receivers, pointing devices and telecom processors. the eprom technology makes customizing application programs (transmitter codes, motor speeds, receiver frequen- cies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mount- ing, make this microcontroller series perfect for applica- tions with space limitations. low cost, low power, high performance ease of use and i/o flexibility make the pic16c5x series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ?glue? logic in larger systems, co-processor applications). 8-bit eprom/rom-based cmos microcontrollers
pic16c5x ds30453e-page 6 preliminary ? 1997-2013 microchip technology inc. table 1-1: pic16c5x family of devices features pic16c54 pic16cr54 pic16c55 pic16c56 pic16cr56 maximum operation frequency 40 mhz 20 mhz 40 mhz 40 mhz 20 mhz eprom program memory (x12 words) 512 ? 512 1k ? rom program memory (x12 words) ? 512 ? ? 1k ram data memory (bytes) 25 25 24 25 25 timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 i/o pins 12 12 20 12 12 number of instructions 33 33 33 33 33 packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic ? family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. features pic16c57 pic16cr57 pic16c58 pic16cr58 maximum operation frequency 40 mhz 20 mhz 40 mhz 20 mhz eprom program memory (x12 words) 2k ? 2k ? rom program memory (x12 words) ? 2k ? 2k ram data memory (bytes) 72 72 73 73 timer module(s) tmr0 tmr0 tmr0 tmr0 i/o pins 20 20 12 12 number of instructions 33 33 33 33 packages 28-pin dip, soic; 28-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic ? family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 7 pic16c5x 2.0 pic16c5x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16c5x product identifica- tion system at the back of this data sheet to specify the correct part number. for the pic16c5x family of devices, there are four device types, as indicated in the device number: 1. c , as in pic16 c 54c. these devices have eprom program memory and operate over the standard voltage range. 2. lc , as in pic16 lc 54a. these devices have eprom program memory and operate over an extended voltage range. 3. cr , as in pic16 cr 54a. these devices have rom program memory and operate over the standard voltage range. 4. lcr , as in pic16 lcr 54a. these devices have rom program memory and operate over an extended voltage range. 2.1 uv erasable devices (eprom) the uv erasable versions offered in cerdip pack- ages, are optimal for prototype development and pilot programs. uv erasable devices can be programmed for any of the four oscillator configurations. microchip's picstart ? plus (1) and pro mate ? programmers both support programming of the pic16c5x. third party programmers also are available. refer to the third party guide (ds00104) for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers expecting frequent code changes and updates, or small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must be pro- grammed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and configuration bit options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. please contact your microchip technology sales office for more details. 2.4 serialized quick-turnaround- production (sqtp sm ) devices microchip offers the unique programming service where a few user defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequen- tial. the devices are identical to the otp devices but with all eprom locations and configuration bit options already programmed by the factory. serial programming allows each device to have a unique number which can serve as an entry code, password or id number. 2.5 read only memory (rom) devices microchip offers masked rom versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products. note 1: pic16lc54c and pic16c54a devices require osc2 not to be connected while programming with picstart ? plus programmer.
pic16c5x ds30453e-page 8 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 9 pic16c5x 3.0 architectural overview the high performance of the pic16c5x family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16c5x uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions. consequently, all instructions (33) execute in a single cycle except for program branches. the pic16c54/cr54 and pic16c55 address 512 x 12 of program memory, the pic16c56/cr56 address 1k x 12 of program memory, and the pic16c57/cr57 and pic16c58/cr58 address 2k x 12 of program memory. all program memory is internal. the pic16c5x can directly or indirectly address its register files and data memory. all special function reg- isters including the program counter are mapped in the data memory. the pic16c5x has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic16c5x simple yet efficient. in addition, the learning curve is reduced significantly. the pic16c5x device contains an 8-bit alu and work- ing register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is either a file register or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1 (for pic16c54/56/58) and table 3-2 (for pic16c55/ 57).
pic16c5x ds30453e-page 10 preliminary ? 1997-2013 microchip technology inc. figure 3-1: pic16c5x series block diagram wdt time out 8 stack 1 stack 2 eprom/rom 512 x 12 to 2048 x 12 instruction register instruction decoder watchdog timer configuration word oscillator/ timing & control general purpose register file (sram) 24, 25, 72 or 73 bytes wdt/tmr0 prescaler option reg. ?option? ?sleep? ?code protect? ?osc select? direct address tmr0 from w from w ?tris 5? ?tris 6? ?tris 7? fsr trisa porta trisb portc trisc portb from w t0cki pin 9-11 9-11 12 12 8 w 4 4 4 data bus 8 8 8 8 8 8 8 alu status from w clkout 8 9 6 5 5-7 osc1 osc2 mclr literals pc ?disable? 2 ra<3:0> rb<7:0> rc<7:0> (28-pin devices only) direct ram address
? 1997-2013 microchip technology inc. preliminary ds30453e-page 11 pic16c5x table 3-1: pinout description - pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58, pic16cr58 pin name pin number pin buffer description dip soic ssop type type ra0 ra1 ra2 ra3 17 18 1 2 17 18 1 2 19 20 1 2 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 6 7 8 9 10 11 12 13 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 3 3 3 i st clock input to timer0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr /v pp 4 4 4 i st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. voltage on the mclr /v pp pin must not exceed v dd to avoid unin- tended entering of programming mode. osc1/clkin 16 16 18 i st oscillator crystal input/external clock source input. osc2/clkout 15 15 17 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. v dd 14 14 15,16 p ? positive supply for logic and i/o pins. v ss 5 5 5,6 p ? ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input
pic16c5x ds30453e-page 12 preliminary ? 1997-2013 microchip technology inc. table 3-2: pinout description - pic16c55, pic16c57, pic16cr57 pin name pin number pin type buffer type description dip soic ssop ra0 ra1 ra2 ra3 6 7 8 9 6 7 8 9 5 6 7 8 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 10 11 12 13 14 15 16 17 10 11 12 13 14 15 16 17 9 10 11 12 13 15 16 17 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 1 1 2 i st clock input to timer0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr 28 28 28 i st master clear (reset) input. this pin is an active low reset to the device. osc1/clkin 27 27 27 i st oscillator crystal input/external clock source input. osc2/clkout 26 26 26 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. v dd 2 2 3,4 p ? positive supply for logic and i/o pins. v ss 4 4 1,14 p ? ground reference for logic and i/o pins. n/c 3,5 3,5 ? ? ? unused, do not connect. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input
? 1997-2013 microchip technology inc. preliminary ds30453e-page 13 pic16c5x 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter is incremented every q1 and the instruc- tion is fetched from program memory and latched into the instruction register in q4. it is decoded and exe- cuted during the following q1 through q4. the clocks and instruction execution flow are shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register in cycle q1. this instruc- tion is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (oper- and read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw h'55' fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
pic16c5x ds30453e-page 14 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 15 pic16c5x 4.0 oscillator configurations 4.1 oscillator types pic16c5xs can be operated in four different oscillator modes. the user can program two configuration bits (fosc1:fosc0) to select one of these four modes: 1. lp: low power crystal 2. xt: crystal/resonator 3. hs: high speed crystal/resonator 4. rc: resistor/capacitor 4.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 4-1). the pic16c5x oscillator design requires the use of a paral- lel cut crystal. use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source drive the osc1/clkin pin (figure 4-2). figure 4-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 4-2: external clock input operation (hs, xt or lp osc configuration) table 4-1: capacitor selection for ceramic resonators - pic16c5x, pic16cr5x table 4-2: capacitor selection for crystal oscillator - pic16c5x, pic16cr5x note: not all oscillator selections available for all parts. see section 9.1. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the oscillator mode cho- sen (approx. value = 10 m ? ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16c5x osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-33 pf 10-22 pf 68-100 pf 15-33 pf 10-22 pf hs 8.0 mhz 16.0 mhz 10-22 pf 10 pf 10-22 pf 10 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type crystal freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15 pf 15 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15 pf 15 pf hs 4 mhz 8 mhz 20 mhz 15 pf 15 pf 15 pf 15 pf 15 pf 15 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. note: if you change from this device to another device, please verify oscillator characteris- tics in your application. clock from ext. system osc1 osc2 pic16c5x open
pic16c5x ds30453e-page 16 preliminary ? 1997-2013 microchip technology inc. 4.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crys- tal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well- designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 4-3 shows an implementation example of a par- allel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 4-3: example of external parallel resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) figure 4-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator cir- cuit. the 330 k ? resistors provide the negative feed- back to bias the inverters in their linear region. figure 4-4: example of external series resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c5x clkin to o t h e r devices osc2 open 330k 74as04 74as04 pic16c5x clkin to other devices xtal 330k 74as04 0.1 ? f osc2 open
? 1997-2013 microchip technology inc. preliminary ds30453e-page 17 pic16c5x 4.4 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 4-5 shows how the r/c combination is con- nected to the pic16c5x. for r ext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ? ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. the electrical specifications sections show rc fre- quency variation from part to part due to normal pro- cess variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications sections for vari- ation of oscillator frequency due to v dd for given r ext / c ext values as well as frequency variation due to oper- ating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic. figure 4-5: rc oscillator mode note: if you change from this device to another device, please verify oscillator characteris- tics in your application. v dd r ext c ext v ss osc1 internal clock osc2/clkout fosc/4 pic16c5x n
pic16c5x ds30453e-page 18 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 19 pic16c5x 5.0 reset pic16c5x devices may be reset in one of the follow- ing ways: ? power-on reset (por) ?mclr reset (normal operation) ?mclr wake-up reset (from sleep) ? wdt reset (normal operation) ? wdt wake-up reset (from sleep) table 5-1 shows these reset conditions for the pcl and status registers. some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset (por), mclr or wdt reset. a mclr or wdt wake-up from sleep also results in a device reset, and not a continuation of operation before sleep. the to and pd bits (status <4:3>) are set or cleared depending on the different reset conditions (table 5- 1). these bits may be used to determine the nature of the reset. table 5-3 lists a full description of reset states of all registers. figure 5-1 shows a simplified block diagram of the on-chip reset circuit. table 5-1: status bits and their significance table 5-2: summary of registers associated with reset condition to pd power-on reset 11 mclr reset (normal operation) uu mclr wake-up (from sleep) 10 wdt reset (normal operation) 01 wdt wake-up (from sleep) 00 legend: u = unchanged, x = unknown, ? = unimplemented read as '0'. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on mclr and wdt reset 03h status pa2 pa1 pa0 to pd z dc c 0001 1xxx 000q quuu legend: u = unchanged, x = unknown, q = see table 5-1 for possible values.
pic16c5x ds30453e-page 20 preliminary ? 1997-2013 microchip technology inc. table 5-3: reset conditions for all registers figure 5-1: simplified block diagram of on-chip reset circuit register address power-on reset mclr or wdt reset wn/a xxxx xxxx uuuu uuuu tris n/a 1111 1111 1111 1111 option n/a --11 1111 --11 1111 indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl 02h 1111 1111 1111 1111 status 03h 0001 1xxx 000q quuu fsr (1) 04h 1xxx xxxx 1uuu uuuu porta 05h ---- xxxx ---- uuuu portb 06h xxxx xxxx uuuu uuuu portc (2) 07h xxxx xxxx uuuu uuuu general purpose register files 07-7fh xxxx xxxx uuuu uuuu legend: x = unknown u = unchanged - = unimplemented, read as '0' q = see tables in table 5-1 for possible values. note 1: these values are valid for pic16c57/cr57/c58/cr58. for the pic16c54/cr54/c55/c56/cr56, the value on reset is 111x xxxx and for mclr and wdt reset, the value is 111u uuuu. 2: general purpose register file on pic16c54/cr54/c56/cr56/c58/cr58. 8-bit asynch ripple counter (device reset sq r q v dd mclr /v pp pin power-up detect on-chip rc osc por (power-on reset) wdt time-out reset chip reset wdt timer)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 21 pic16c5x 5.1 power-on reset (por) the pic16c5x family incorporates on-chip power-on reset (por) circuitry which provides an internal chip reset for most power-up situations. to use this fea- ture, the user merely ties the mclr /v pp pin to v dd . a simplified block diagram of the on-chip power-on reset circuit is shown in figure 5-1. the power-on reset circuit and the device reset timer (section 5.2) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is not tied to v dd is shown in figure 5-3. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 5-4, the on-chip power-on reset feature is being used (mclr and v dd are tied together). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 5-5 depicts a problem situation where v dd rises too slowly. the time between when the drt senses a high on the mclr /v pp pin, and when the mclr /v pp pin (and v dd ) actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function correctly. for such situations, we recommend that external rc cir- cuits be used to achieve longer por delay times (figure 5-2). for more information on pic16c5x por, see power- up considerations - an522 in the embedded control handbook . the por circuit does not produce an internal reset when v dd declines. figure 5-2: external power-on reset circuit (for slow vdd power-up) note: when the device starts normal operation (exits the reset condition), device oper- ating parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. c r1 r d mclr pic16c5x v dd v dd ? external power-on reset circuit is required only if v dd power-up is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. ?r < 40k ? is recommended to make sure that voltage drop across r does not violate the device electrical specification. ?r1 = 100 ? to 1 k ? will limit any current flow- ing into mclr from external capacitor c in the event of mclr pin breakdown due to electro- static discharge (esd) or electrical over- stress (eos).
pic16c5x ds30453e-page 22 preliminary ? 1997-2013 microchip technology inc. figure 5-3: time-out sequ ence on power-up (mclr not tied to vdd) figure 5-4: time-out sequ ence on power-up (mclr tied to vdd): fast vdd rise time figure 5-5: time-out sequ ence on power-up (mclr tied to vdd): slow vdd rise time v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 ? v dd min t drt
? 1997-2013 microchip technology inc. preliminary ds30453e-page 23 pic16c5x 5.2 device reset timer (drt) the device reset timer (drt) provides an 18 ms nominal time-out on reset regardless of oscillator mode used. the drt operates on an internal rc oscil- lator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after the voltage on the mclr /v pp pin has reached a logic high (v ih ) level. thus, external rc networks connected to the mclr input are not required in most cases, allow- ing for savings in cost-sensitive and/or space restricted applications. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out. this is particularly important for applications using the wdt to wake the pic16c5x from sleep mode automatically. 5.3 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16c5x devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 5-6, figure 5-7 and figure 5- 8. figure 5-6: exte rnal brown-out protection circuit 1 figure 5-7: external brown-out protection circuit 2 figure 5-8: external brown-out protection circuit 3 this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 33k 10k 40k v dd mclr pic16c5x v dd q1 this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd ? r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16c5x r1 q1 v dd this brown-out protection circuit employs micro- chip technology?s mcp809 microcontroller supervisor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collec- tor outputs with both "active high and active low" reset pins. there are 7 different trip point selec- tions to accommodate 5v and 3v systems. mclr pic16c5x v dd vss rst mcp809 v dd bypass capacitor v dd
pic16c5x ds30453e-page 24 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 25 pic16c5x 6.0 memory organization pic16c5x memory is organized into program memory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one or two status register bits. for devices with a data memory register file of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file selection register (fsr). 6.1 program memory organization the pic16c54, pic16cr54 and pic16c55 have a 9- bit program counter (pc) capable of addressing a 512 x 12 program memory space (figure 6-1). the pic16c56 and pic16cr56 have a 10-bit program counter (pc) capable of addressing a 1k x 12 program memory space (figure 6-2). the pic16cr57, pic16c58 and pic16cr58 have an 11-bit program counter capable of addressing a 2k x 12 program memory space (figure 6-3). accessing a location above the physically implemented address will cause a wraparound. a nop at the reset vector location will cause a restart at location 000h. the reset vector for the pic16c54, pic16cr54 and pic16c55 is at 1ffh. the reset vector for the pic16c56 and pic16cr56 is at 3ffh. the reset vector for the pic16c57, pic16cr57, pic16c58, and pic16cr58 is at 7ffh. see section 6.5 for additional information using call and goto instructions. figure 6-1: pic16c54/cr54/c55 program memory map and stack figure 6-2: pic16c56/cr56 program memory map and stack figure 6-3: pic16c57/cr57/c58/ cr58 program memory map and stack pc<8:0> stack level 1 stack level 2 user memory space call, retlw 9 000h 1ffh reset vector 0ffh 100h on-chip program memory pc<9:0> stack level 1 stack level 2 user memory space 10 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) 200h 2ffh 300h 3ffh call, retlw pc<10:0> stack level 1 stack level 2 user memory space 11 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) on-chip program memory (page 2) on-chip program memory (page 3) 200h 3ffh 2ffh 300h 400h 5ffh 4ffh 500h 600h 7ffh 6ffh 700h call, retlw
pic16c5x ds30453e-page 26 preliminary ? 1997-2013 microchip technology inc. 6.2 data memory organization data memory is composed of registers, or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers and gen- eral purpose registers. the special function registers include the tmr0 reg- ister, the program counter (pc), the status register, the i/o registers (ports) and the file select register (fsr). in addition, special purpose registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic16c54, pic16cr54, pic16c56 and pic16cr56, the register file is composed of 7 special function registers and 25 general purpose registers (figure 6-4). for the pic16c55, the register file is composed of 8 special function registers and 24 general purpose registers. for the pic16c57 and pic16cr57, the register file is composed of 8 special function registers, 24 general purpose registers and up to 48 additional general purpose registers that may be addressed using a banking scheme (figure 6-5). for the pic16c58 and pic16cr58, the register file is composed of 7 special function registers, 25 general purpose registers and up to 48 additional general purpose registers that may be addressed using a banking scheme (figure 6-6). 6.2.1 general purpose register file the register file is accessed either directly or indirectly through the file select register (fsr). the fsr reg- ister is described in section 6.7. figure 6-4: pic16c54, pic16cr54, pic16c55, pic16c56, pic16cr56 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb general purpose registers note 1: not a physical register. see section 6.7. 2: pic16c55 only, in all other devices this is implemented as a a general purpose register. portc (2) 08h
? 1997-2013 microchip technology inc. preliminary ds30453e-page 27 pic16c5x figure 6-5: pic16c57/cr57 register file map figure 6-6: pic16c58/cr58 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb 0fh 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 2fh 5fh 50h 40h 4fh 7fh 70h 60h 6fh general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers portc 08h addresses map back to addresses in bank 0. note 1: not a physical register. see section 6.7. fsr<6:5> 00 01 10 11 file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb 0fh 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 2fh 5fh 50h 40h 4fh 7fh 70h 60h 6fh general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 6.7. fsr<6:5> 00 01 10 11
pic16c5x ds30453e-page 28 preliminary ? 1997-2013 microchip technology inc. 6.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions to control the opera- tion of the device (table 6-1). the special registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 6-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset details on page n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 35 n/a option contains control bits to configure timer0 and timer0/wdt prescaler --11 1111 30 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 32 01h tmr0 timer0 module register xxxx xxxx 38 02h (1) pcl low order 8 bits of pc 1111 1111 31 03h status pa2 pa1 pa0 to pd zdcc 0001 1xxx 29 04h fsr indirect data memory address pointer 1xxx xxxx (3) 32 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx 35 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 35 07h (2) portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 35 legend: x = unknown, u = unchanged, ? = unimplemented, read as '0' (if applicable). shaded cells = unimplemented or unused note 1: the upper byte of the program counter is not directly ac cessible. see section 6.5 for an explanation of how to access these bits. 2: file address 07h is a general purpose register on the pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58 and pic16cr58. 3: these values are valid for pic16c57/cr57/c58/cr58. for the pic16c54/cr54/c55/c56/cr56, the value on reset is 111x xxxx and for mclr and wdt reset, the value is 111u uuuu.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 29 pic16c5x 6.3 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bits for pro- gram memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status reg- ister because these instructions do not affect the z, dc or c bits from the status register. for other instruc- tions which do affect status bits, see section 10.0, instruction set summary. register 6-1: status register (address: 03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x pa2 pa1 pa0 to pd zdcc bit 7 bit 0 bit 7: pa2 : this bit unused at this time. use of the pa2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: pa<1:0> : program page preselect bits (pic16c56/cr56)(pic16c57/cr57)(pic16c58/cr58) 00 = page 0 (000h - 1ffh) - pic16c56/cr56, pic16c57/cr57, pic16c58/cr58 01 = page 1 (200h - 3ffh) - pic16c56/cr56, pic16c57/cr57, pic16c58/cr58 10 = page 2 (400h - 5ffh) - pic16c57/cr57, pic16c58/cr58 11 = page 3 (600h - 7ffh) - pic16c57/cr57, pic16c58/cr58 each page is 512 words. using the pa<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur loaded with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
pic16c5x ds30453e-page 30 preliminary ? 1997-2013 microchip technology inc. 6.4 option register the option register is a 6-bit wide, write-only regis- ter which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option reg- ister. a reset sets the option<5:0> bits. register 6-2: option register u-0 u-0 w-1 w-1 w-1 w-1 w-1 w-1 ? ? t0cs tose psa ps2 ps1 ps0 bit 7 bit 0 bit 7-6: unimplemented : read as ?0? bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps<2:0> : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 1997-2013 microchip technology inc. preliminary ds30453e-page 31 pic16c5x 6.5 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next pro- gram instruction to be executed. the pc value is increased by one, every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0> (figure 6-7, figure 6-8 and figure 6-9). for the pic16c56, pic16cr56, pic16c57, pic16cr57, pic16c58 and pic16cr58, a page num- ber must be supplied as well. bit5 and bit6 of the sta- tus register provide page information to bit9 and bit10 of the pc (figure 6-8 and figure 6-9). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are pro- vided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 6-7 and figure 6-8). instructions where the pcl is the destination, or modify pcl instructions, include movwf pcl, addwf pcl, and bsf pcl,5. for the pic16c56, pic16cr56, pic16c57, pic16cr57, pic16c58 and pic16cr58, a page num- ber again must be supplied. bit5 and bit6 of the sta- tus register provide page information to bit9 and bit10 of the pc (figure 6-8 and figure 6-9). figure 6-7: loading of pc branch instructions - pic16c54, pic16cr54, pic16c55 figure 6-8: loading of pc branch instructions - pic16c56/pic16cr56 figure 6-9: loading of pc branch instructions - pic16c57/pic16cr57, and pic16c58/ pic16cr58 note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). pc 87 0 pcl pc 87 0 pcl reset to '0' instruction word instruction word goto instruction call or modify pcl instruction pa<1:0> 2 status pc 87 0 pcl 9 10 pa<1:0> 2 status pc 87 0 pcl 9 10 instruction word reset to ?0? instruction word 70 70 goto instruction call or modify pcl instruction 0 0 0 0 pa<1:0> 2 status pc 87 0 pcl 9 10 pa<1:0> 2 status pc 87 0 pcl 9 10 instruction word reset to ?0? instruction word 70 70 goto instruction call or modify pcl instruction
pic16c5x ds30453e-page 32 preliminary ? 1997-2013 microchip technology inc. 6.5.1 paging considerations ? pic16c56/cr56, pic16c57/cr57 and pic16c58/cr58 if the program counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. however, the page preselect bits in the status reg- ister will not be updated. therefore, the next goto , call or modify pcl instruction will send the program to the page specified by the page preselect bits (pa0 or pa<1:0>). for example, a nop at location 1ffh (page 0) incre- ments the pc to 200h (page 1). a goto xxx at 200h will return the program to address xxh on page 0 (assuming that pa<1:0> are clear). to prevent this, the page preselect bits must be updated under program control. 6.5.2 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the reset vector). the status register page preselect bits are cleared upon a reset, which means that page 0 is pre- selected. therefore, upon a reset, a goto instruction at the reset vector location will automatically cause the pro- gram to jump to page 0. 6.6 stack pic16c5x devices have a 10-bit or 11-bit wide, two- level hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program coun- ter value, incremented by one, into stack level 1. if more than two sequential call ?s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw ?s are executed, the stack will be filled with the address previously stored in level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the pro- gram memory. for the retlw instruction, the pc is loaded with the top of stack (tos) contents. all of the devices covered in this data sheet have a two-level stack. the stack has the same bit width as the device pc, therefore, paging is not an issue when returning from a subroutine.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 33 pic16c5x 6.7 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 6-1: indirect addressing ? register file 08 contains the value 10h ? register file 09 contains the value 0ah ? load the value 08 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 09h) ? a read of the indf register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 6-2. example 6-2: how to clear ram using indirect addressing movlw h'10' ;in itialize pointer movwf fsr ; to ram next clrf indf ;cl ear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is either a 5-bit (pic16c54, pic16cr54, pic16c55, pic16c56, pic16cr56) or 7-bit (pic16c57, pic16cr57, pic16c58, pic16cr58) wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic16c54, pic16cr54, pic16c55, pic16c56 , pic16cr56: these do not use banking. fsr<6:5> bits are unimplemented and read as '1's. pic16c57, pic16cr57, pic16c58, pic16cr58: fsr<6:5> are the bank select bits and are used to select the bank to be addressed ( 00 = bank 0, 01 =bank 1, 10 = bank 2, 11 = bank 3). figure 6-10: direct/indirect addressing note 1: for register map detail see section 6.2. bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 bank 2 bank 3 0 4 5 6 (fsr) 10 00 01 11 00h 1fh 3fh 5fh 7fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0. 3 2 1 3 2 1
pic16c5x ds30453e-page 34 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 35 pic16c5x 7.0 i/o ports as with any other register, the i/o registers can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance) since the i/o control registers (trisa, trisb, trisc) are all set. 7.1 porta porta is a 4-bit i/o register. only the low order 4 bits are used (ra<3:0>). bits 7-4 are unimplemented and read as '0's. 7.2 portb portb is an 8-bit i/o register (portb<7:0>). 7.3 portc portc is an 8-bit i/o register for pic16c55, pic16c57 and pic16cr57. portc is a general purpose register for pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58 and pic16cr58. 7.4 tris registers the output driver control registers are loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance (input) mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the tris registers are ?write-only? and are set (output drivers disabled) upon reset. 7.5 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 7-1. all ports may be used for both input and output operation. for input operations these ports are non-latching. any input must be present until read by an input instruction (e.g., movf portb, w ). the out- puts are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corre- sponding direction control bit (in trisa, trisb, trisc) must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin can be programmed individually as input or output. figure 7-1: equivalent circuit for a single i/o pin table 7-1: summary of port registers note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck p n wr port tris ?f? data tris rd port v ss v dd i/o pin (1) w reg latch latch reset address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as '0', shaded cells = unimplemented, read as ?0?
pic16c5x ds30453e-page 36 preliminary ? 1997-2013 microchip technology inc. 7.6 i/o programming considerations 7.6.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu, bit5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bi-direc- tional i/o pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 7-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired-or?, ?wired-and?). the resulting high output currents may damage the chip. example 7-1: read-modify-write instructions on an i/o port ;initial port settings ; portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ;01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp movlw h'3f' ; tris portb ;10pp pppp 10pp pppp ; ;note that the user may have expected the pin ;values to be 00pp pppp. the 2nd bcf caused ;rb7 to be latched as the pin value (high). 7.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 7- 2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin volt- age to stabilize (load dependent) before the next instruction, which causes that file to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instruc- tions with a nop or another instruction not accessing this i/o port. figure 7-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<7:0> movwf portb nop port pin sampled here nop movf portb,w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. (read portb) port pin written here
? 1997-2013 microchip technology inc. preliminary ds30453e-page 37 pic16c5x 8.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 - readable and writable ? 8-bit software programmable prescaler ? internal or external clock select - edge select for external clock figure 8-1 is a simplified block diagram of the timer0 module, while figure 8-2 shows the electrical structure of the timer0 input. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 8-3 and figure 8-4). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the incrementing edge is determined by the source edge select bit t0se (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 8.1. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 8.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 8-1. figure 8-1: timer0 block diagram figure 8-2: electrical structure of t0cki pin note: the prescaler may be used by either the timer0 module or the watchdog timer, but not both. note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register (section 6.4). 2: the prescaler is shared with the watchdog timer (figure 8-6). t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync v ss v ss r in schmitt trigger n input buffer t0cki pin note 1: esd protection circuits. (1) (1)
pic16c5x ds30453e-page 38 preliminary ? 1997-2013 microchip technology inc. figure 8-3: timer0 timing: inte rnal clock/no prescaler figure 8-4: timer0 timing: inte rnal clock/prescaler 1:2 table 8-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option ? ? t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented. shaded cells not used by timer0. pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0
? 1997-2013 microchip technology inc. preliminary ds30453e-page 39 pic16c5x 8.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 8.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 8-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical specification of the desired device. 8.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 8-5 shows the delay from the external clock edge to the timer incrementing. figure 8-5: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (2) prescaler output (1) (3) note 1: external clock if no prescaler selected, prescaler output otherwise. 2: the arrows indicate the points in time where sampling occurs. 3: delay from clock input change to timer0 increment is 3tosc to 7tosc (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = ? 4tosc max.
pic16c5x ds30453e-page 40 preliminary ? 1997-2013 microchip technology inc. 8.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt), respectively (section 9.2.1). for simplic- ity, this counter is being referred to as ?prescaler? throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is nei- ther readable nor writable. on a reset, the prescaler contains all '0's. 8.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ?on the fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 8-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 8-1: changing prescaler (timer0 ? wdt) clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw b'00xx1111? ;last 3 instructions in this example option ;are required only if ;desired clrwdt ;ps<2:0> are 000 or ;001 movlw b'00xx1xxx? ;set prescaler to option ;desired wdt rate to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 8-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switch- ing the prescaler. example 8-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option
? 1997-2013 microchip technology inc. preliminary ds30453e-page 41 pic16c5x figure 8-6: block diag ram of the timer0/wdt prescaler t0cki t0se pin t cy ( = f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x
pic16c5x ds30453e-page 42 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 43 pic16c5x 9.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. the pic16c5x family of microcon- trollers have a host of such features intended to maxi- mize system reliability, minimize cost through elimination of external components, provide power sav- ing operating modes and offer code protection. these features are: ? oscillator selection (section 4.0) ? reset (section 5.0) ? power-on reset (section 5.1) ? device reset timer (section 5.2) ? watchdog timer (wdt) (section 9.2) ? sleep (section 9.3) ? code protection (section 9.4) ? id locations (section 9.5) the pic16c5x family has a watchdog timer which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. there is an 18 ms delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low cur- rent power-down mode. the user can wake up from sleep through external reset or through a watch- dog timer time-out. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options.
pic16c5x ds30453e-page 44 preliminary ? 1997-2013 microchip technology inc. 9.1 configuration bits configuration bits can be programmed to select various device configurations. two bits are for the selection of the oscillator type and one bit is the watchdog timer enable bit. nine bits are code protection bits for the pic16c54a, pic16cr54a, pic16c54c, pic16cr54c, pic16c55a, pic16c56a, pic16cr56a, pic16c57c, pic16cr57c, pic16c58b, and pic16cr58b devices (register 9-1). one bit is for code protection for the pic16c54, pic16c55, pic16c56 and pic16c57 devices (register 9-2). qtp or rom devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "product identification system" dia- grams in the back of this data sheet). register 9-1: configuration word for pic16c54a/cr54a/c54c/cr54c/c55a/c56a/ cr56a/c57c/cr57c/c58b/cr58b cp cp cp cp cp cp cp cp cp wdte fosc1 fosc0 bit 11 bit 0 bit 11-3: cp : code protection bit 1 = code protection off 0 = code protection on bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bit 00 = lp oscillator 01 = xt oscillator 10 = hs oscillator 11 = rc oscillator note 1: refer to the pic16c5x programming specification (literature number ds30190) to determine how to access the configuration word. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
? 1997-2013 microchip technology inc. preliminary ds30453e-page 45 pic16c5x register 9-2: configuration word fo r pic16c54/c55/c56/c57 ? ? ? ? ? ? ? ? cp wdte fosc1 fosc0 bit 11 bit 0 bit 11-4: unimplemented : read as ?0? bit 3: cp: code protection bit. 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits (2) 00 = lp oscillator 01 = xt oscillator 10 = hs oscillator 11 = rc oscillator note 1: refer to the pic16c5x programming specifications (literature number ds30190) to determine how to access the configuration word. 2: pic16lv54a supports xt, rc and lp oscillator only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown
pic16c5x ds30453e-page 46 preliminary ? 1997-2013 microchip technology inc. 9.2 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external com- ponents. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins have been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watch- dog timer reset (section 6.3). the wdt can be permanently disabled by program- ming the configuration bit wdte as a '0' (section 9.1). refer to the pic16c5x programming specifications (literature number ds30190) to determine how to access the configuration word. 9.2.1 wdt period an 8-bit counter is available as a prescaler for the timer0 module (section 8.2), or as a postscaler for the watchdog timer (wdt), respectively. for simplicity, this counter is being referred to as ?prescaler? through- out this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio (section 6.4). the wdt has a nominal time-out period of 18 ms (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writ- ing to the option register. thus, time-out a period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see device characterization). under worst case conditions (v dd = min., temperature = max., wdt prescaler = 1:128), it may take several seconds before a wdt time-out occurs. 9.2.2 wdt programming considerations the clrwdt instruction clears the wdt and the pres- caler, if assigned to the wdt, and prevents it from tim- ing out and generating a device reset. the sleep instruction resets the wdt and the pres- caler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. figure 9-1: watchdog timer block diagram table 9-1: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a option ? ? tos c tose psa ps2 ps1 ps0 --11 1111 --11 1111 legend: u = unchanged, - = unimplemented, read as '0'. shaded cells not used by watchdog timer. 1 0 1 0 from tmr0 clock source to t m r 0 wdt enable eprom bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux m u x watchdog timer note: t0cs, t0se, psa, ps2:ps0 are bits in the option register. prescaler
? 1997-2013 microchip technology inc. preliminary ds30453e-page 47 pic16c5x 9.3 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 9.3.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr /v pp pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the mclr /v pp pin must be at a logic high level (mclr = v ih ). 9.3.2 wake-up from sleep the device can wake up from sleep through one of the following events: 1. an external reset input on mclr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). both of these events cause a device reset. the to and pd bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time- out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. 9.4 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 9.5 id locations four memory locations are designated as id locations where the user can store checksum or other code-iden- tification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as '1's. note: microchip does not recommend code pro- tecting windowed devices. note: microchip will assign a unique pattern number for qtp and sqtp requests and for rom devices. this pattern number will be unique and traceable to the submitted code.
pic16c5x ds30453e-page 48 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 49 pic16c5x 10.0 instruction set summary each pic16c5x instruction is a 12-bit word divided into an opcode, which specifies the instruction type and one or more operands which further specify the opera- tion of the instruction. the pic16c5x instruction set summary in table 10-2 groups the instructions into byte-oriented, bit-oriented, and literal and control oper- ations. table 10-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator is used to specify which one of the 32 file registers in that bank is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is '0', the result is placed in the w register. if 'd' is '1', the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. table 10-1: opcode field descriptions all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time would be 1 ? s. if a condi- tional test is true or the program counter is changed as a result of an instruction, the instruction execution time would be 2 ? s. figure 10-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal num- ber: 0xhhh where 'h' signifies a hexadecimal digit. figure 10-1: general format for instructions field description f register file address (0x00 to 0x1f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for com- patibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register 'f') default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic16c5x ds30453e-page 50 preliminary ? 1997-2013 microchip technology inc. table 10-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k k k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto (see section 6.5 for more on program counter). 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 5, 6 or 7 causes the contents of the w register to be written to the tristate latches of porta, b or c respectively. a '1' forces the pin to a hi-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
? 1997-2013 microchip technology inc. preliminary ds30453e-page 51 pic16c5x addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 31 d ??????? operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f'. words: 1 cycles: 1 example: addwf temp_reg, 0 before instruction w =0x17 temp_reg = 0xc2 after instruction w=0xd9 temp_reg = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w).and. (k) ? (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are and?ed with the eight-bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: andlw h'5f' before instruction w=0xa3 after instruction w=0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 31 d ??????? operation: (w) .and. (f) ? (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are and?ed with register 'f'. if 'd' is 0 the result is stored in the w regis- ter. if 'd' is '1' the result is stored back in register 'f'. words: 1 cycles: 1 example: andwf temp_reg, 1 before instruction w=0x17 temp_reg = 0xc2 after instruction w =0x17 temp_reg = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 0 ? (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic16c5x ds30453e-page 52 preliminary ? 1997-2013 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 1 ? (f) status affected: none encoding: 0101 bbbf ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit 'b' in register 'f' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2-cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (true) ; if flag<1> = 1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 31 0 ? b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2-cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true ?? ?? ? before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1> = 1, pc = address (true)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 53 pic16c5x call subroutine call syntax: [ label ] call k operands: 0 ? k ? 255 operation: (pc) + 1 ? tos; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two- cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 31 operation: 00h ? (f); 1 ? z status affected: z encoding: 0000 011f ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w=0x5a after instruction w=0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? to; 1 ? pd status affected: to , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler = 0 to =1 pd =1
pic16c5x ds30453e-page 54 preliminary ? 1997-2013 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 0010 01df ffff description: the contents of register 'f' are complemented. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? (dest) status affected: z encoding: 0000 11df ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register 'f' are dec- remented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt ? 0, pc = address (here+1)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 55 pic16c5x goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two- cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 0010 10df ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two- cycle instruction. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt ? 0, pc = address (here +1)
pic16c5x ds30453e-page 56 preliminary ? 1997-2013 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. (k) ? (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are or?ed with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: iorlw 0x35 before instruction w= 0x9a after instruction w= 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 0010 00df ffff description: the contents of register 'f' is moved to destination 'd'. if 'd' is 0, destination is the w register. if 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal 'k' is loaded into the w register. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a
? 1997-2013 microchip technology inc. preliminary ds30453e-page 57 pic16c5x movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 31 operation: (w) ? (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to register 'f'. words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ? ;w now has table ? ;value. ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w=0x07 after instruction w = value of k8
pic16c5x ds30453e-page 58 preliminary ? 1997-2013 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag (status<0>). if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 c register 'f' rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag (status<0>). if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; if assigned 1 ? to ; 0 ? pd status affected: to , pd encoding: 0000 0000 0011 description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. the wdt and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section on sleep for more details. words: 1 cycles: 1 example: sleep c register 'f'
? 1997-2013 microchip technology inc. preliminary ds30453e-page 59 pic16c5x subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 31 d ? [0,1] operation: (f) ? (w) ??? dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2?s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive example 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero example 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0 ; result is negative swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w=0x5a tris load tris register syntax: [ label ] tris f operands: f = 5, 6 or 7 operation: (w) ? tris register f status affected: none encoding: 0000 0000 0fff description: tris register 'f' (f = 5, 6, or 7) is loaded with the contents of the w register. words: 1 cycles: 1 example tris portb before instruction w=0xa5 after instruction trisb = 0xa5
pic16c5x ds30453e-page 60 preliminary ? 1997-2013 microchip technology inc. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: xorlw 0xaf before instruction w=0xb5 after instruction w=0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w) .xor. (f) ??? dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w regis- ter. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
? 1997-2013 microchip technology inc. preliminary ds30453e-page 61 pic16c5x 11.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 11.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (auto- matically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 11.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 11.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ?c? compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c5x ds30453e-page 62 preliminary ? 1997-2013 microchip technology inc. 11.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 11.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 11.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 11.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 63 pic16c5x 11.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic mcus and can be used to develop for this and other pic microcontrollers. the mplab icd utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 11.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 11.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 11.11 picdem 1 low cost pic mcu demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip?s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 11.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c5x ds30453e-page 64 preliminary ? 1997-2013 microchip technology inc. 11.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 11.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 11.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip?s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 65 pic16c5x table 11-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment ??????????????? mplab ? c17 c compiler ?? mplab ? c18 c compiler ?? mpasm tm assembler/ mplink tm object linker ??????????????? ? ? emulators mplab ? ice in-circuit emulator ??? ? ?? ** ????????? icepic tm in-circuit emulator ? ??? ??? ? debugger mplab ? icd in-circuit debugger ? * ? * ?? programmers picstart ? plus entry level development programmer ??? ? ?? ** ????????? pro mate ? ii universal device programmer ??? ? ?? ** ????????? ? ? demo boards and eval kits picdem tm 1 demonstration board ??? ? ?? picdem tm 2 demonstration board ? ? ? ? ?? picdem tm 3 demonstration board ? picdem tm 14a demonstration board ? picdem tm 17 demonstration board ? k ee l oq ? evaluation kit ? k ee l oq ? transponder kit ? microid tm programmer?s kit ? 125 khz microid tm developer?s kit ? 125 khz anticollision microid tm developer?s kit ? 13.56 mhz anticollision microid tm developer?s kit ? mcp2510 can developer?s kit ? * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c5x ds30453e-page 66 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 67 pic16c5x 12.0 electrical characteristics - pic16c54a absolute maximum ratings (?) ambient temperature under bias ................................................................................................. .... ?55c to +125c storage temperature ............................................................................................................ ........... ?65c to +150c voltage on v dd with respect to v ss ..........................................................................................................0v to +7.5v voltage on mclr with respect to v ss (1) ....................................................................................................0v to +14v voltage on all other pins with respect to v ss ............................................................................?0.6v to (v dd + 0.6v) total power dissipation (2) ............................................................................................................................... 800 mw max. current out of v ss pin ........................................................................................................................... .. 150 ma max. current into v dd pin ........................................................................................................................... ..... 100 ma max. current into an input pin (t0cki only).................................................................................... ................ 500 ? a input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................. 20 ma max. output current sunk by any i/o pin ........................................................................................ ................... 25 ma max. output current sourced by any i/o pin ..................................................................................... ................. 20 ma max. output current sourced by a single i/o port (porta, b or c) ............................................................... ... 40 ma max. output current sunk by a single i/o port (porta, b or c).................................................................. ...... 50 ma note 1: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50 to 100 ? should be used when applying a ?low? level to the mclr pin rather than pulling this pin directly to v ss . 2: power dissipation is calculated as follows: pdis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453e-page 68 preliminary ? 1997-2013 microchip technology inc. 12.1 dc characteristics: pic16c54/55/56/57-rc, xt, 10, hs, lp (commercial) pic16c54/55/56/57-rc, xt, 10, hs, lp (commercial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial param no. symbol characteristic/device min typ? max units conditions d001 v dd supply voltage pic16c5x-rc pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-lp 3.0 3.0 4.5 4.5 2.5 ? ? ? ? ? 6.25 6.25 5.5 5.5 6.25 v v v v v d002 v dr ram data retention voltage (1) 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) pic16c5x-rc (3) pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-hs pic16c5x-lp ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 32 ma ma ma ma ma ? a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled d020 i pd power-down current (2) ? ? 4.0 0.6 12 9 ? a ? a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. ? data in ?typ? column is based on characterization results at 25 ? c. ? this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 69 pic16c5x 12.2 dc characteristics: pic16c54/55/56/57-rci, xti, 10i, hsi, lpi (industrial) pic16c54/55/56/57-rci, xti, 10i, hsi, lpi (industrial) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions d001 v dd supply voltage pic16c5x-rci pic16c5x-xti pic16c5x-10i pic16c5x-hsi pic16c5x-lpi 3.0 3.0 4.5 4.5 2.5 ? ? ? ? ? 6.25 6.25 5.5 5.5 6.25 v v v v v d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) pic16c5x-rci (3) pic16c5x-xti pic16c5x-10i pic16c5x-hsi pic16c5x-hsi pic16c5x-lpi ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 40 ma ma ma ma ma ? a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled d020 i pd power-down curren t (2) ? ? 4.0 0.6 14 12 ? a ? a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. ? data in ?typ? column is based on characterization results at 25 ? c. ? this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 70 preliminary ? 1997-2013 microchip technology inc. 12.3 dc characteristics: pic16c54/55/56/57-rce, xte, 10e, hse, lpe (extended) pic16c54/55/56/57-rce, xte, 10e, hse, lpe (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c for extended param no. symbol characteristic/device min typ? max units conditions d001 v dd supply voltage pic16c5x-rce pic16c5x-xte pic16c5x-10e pic16c5x-hse pic16c5x-lpe 3.25 3.25 4.5 4.5 2.5 ? ? ? ? ? 6.0 6.0 5.5 5.5 6.0 v v v v v d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) pic16c5x-rce (3) pic16c5x-xte pic16c5x-10e pic16c5x-hse pic16c5x-hse pic16c5x-lpe ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 19 3.3 3.3 10 10 20 55 ma ma ma ma ma ? a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.25v, wdt disabled d020 i pd power-down current (2) ? ? 5.0 0.8 22 18 ? a ? a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. ? data in ?typ? column is based on characterization results at 25 ? c. ? this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 71 pic16c5x 12.4 dc characteristics: pic16c54/55/56/57-rc, xt, 10, hs, lp (commercial) pic16c54/55/56/57-rci, xti, 10i, hsi, lpi (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions d030 v il input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 (schmitt trigger) v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (3) pic16c5x-xt, 10, hs, lp d040 v ih input high voltage i/o ports i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 (schmitt trigger) 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (4) 4.0v < v dd ? 5.5v (4) v dd > 5.5v pic16c5x-rc only (3) pic16c5x-xt, 10, hs, lp d050 v hys hysteresis of schmitt trigger inputs 0.15 v dd *? ? v d060 i il input leakage current (1,2) i/o ports mclr mclr t0cki osc1 ?1 ?5 ? ?3 ?3 0.5 ? 0.5 0.5 0.5 +1 ? +5 +3 +3 ? a ? a ? a ? a ? a for v dd ? 5.5v: v ss ? v pin ? v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss ? v pin ? v dd v ss ? v pin ? v dd , pic16c5x-xt, 10, hs, lp d080 v ol output low voltage i/o ports osc2/clkout ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc d090 v oh output high voltage (2) i/o ports osc2/clkout v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ?5.4 ma, v dd = 4.5v i oh = ?1.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25c. this data is for design guidance only and is not tested. note 1: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 2: negative current is defined as coming out of the pin. 3: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 4: the user may use the better of the two specifications.
pic16c5x ds30453e-page 72 preliminary ? 1997-2013 microchip technology inc. 12.5 dc characteristics: pic16c54/55/56/57-rc e, xte, 10e, hse, lpe (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions d030 v il input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 (schmitt trigger) vss vss vss vss vss ? ? ? ? ? 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (3) pic16c5x-xt, 10, hs, lp d040 v ih input high voltage i/o ports i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 (schmitt trigger) 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (4) 4.0v < v dd ? 5.5v (4) v dd > 5.5 v pic16c5x-rc only (3) pic16c5x-xt, 10, hs, lp d050 v hys hysteresis of schmitt trigger inputs 0.15 v dd *? ? v d060 i il input leakage current (1,2) i/o ports mclr mclr t0cki osc1 ?1 ?5 ? ?3 ?3 0.5 ? 0.5 0.5 0.5 +1 ? +5 +3 +3 ? a ? a ? a ? a ? a for v dd ? 5.5 v: v ss ? v pin ? v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss ? v pin ? v dd v ss ? v pin ? v dd , pic16c5x-xt, 10, hs, lp d080 v ol output low voltage i/o ports osc2/clkout ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc d090 v oh output high voltage (2) i/o ports osc2/clkout v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ?5.4 ma, v dd = 4.5v i oh = ?1.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25c. this data is for design guidance only and is not tested. note 1: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 2: negative current is defined as coming out of the pin. 3: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 4: the user may use the better of the two specifications.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 73 pic16c5x 12.6 timing parameter symbology and load conditions the timing parameter symbols have been created with one of the following formats: figure 12-1: load conditions for device timing specifications - pic16c54/55/56/57 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance c l v ss pin c l = 50 pf for all pins and osc2 for rc mode 0 - 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
pic16c5x ds30453e-page 74 preliminary ? 1997-2013 microchip technology inc. 12.7 timing diagrams and specifications figure 12-2: external clock timing - pic16c54/55/56/57 osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2 table 12-1: external clock timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions 1a f osc external clkin frequency (1) dc ? 4.0 mhz xt osc mode dc ? 10 mhz 10 mhz mode dc ? 20 mhz hs osc mode (comm/ind) dc ? 16 mhz hs osc mode (ext) dc ? 40 khz lp osc mode oscillator frequency (1) dc ? 4.0 mhz rc osc mode 0.1 ? 4.0 mhz xt osc mode 4.0 ? 10 mhz 10 mhz mode 4.0 ? 20 mhz hs osc mode (comm/ind) 4.0 ? 16 mhz hs osc mode (ext) dc ? 40 khz lp osc mode * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 75 pic16c5x 1t osc external clkin period (1) 250 ? ? ns xt osc mode 100 ? ? ns 10 mhz mode 50 ? ? ns hs osc mode (comm/ind) 62.5 ? ? ns hs osc mode (ext) 25 ? ? ? slp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 100 ? 250 ns 10 mhz mode 50 ? 250 ns hs osc mode (comm/ind) 62.5 ? 250 ns hs osc mode (ext) 25 ? ? ? slp osc mode 2 tcy instruction cycle time (2) ?4/f osc ?? 3 tosl, to s h clock in (osc1) low or high time 85* ? ? ns xt oscillator 20* ? ? ns hs oscillator 2.0* ? ? ? s lp oscillator 4tosr, to s f clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 25* ns hs oscillator ? ? 50* ns lp oscillator table 12-1: external clock timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x ds30453e-page 76 preliminary ? 1997-2013 microchip technology inc. figure 12-3: clkout and i/o timing - pic16c54/55/56/57 table 12-2: clkout and i/o timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units 10 tosh2ckl osc1 ? to clkout ? (1) ?1530** ns 11 tosh2ckh osc1 ? to clkout ? (1) ?1530** ns 12 tckr clkout rise time (1) ?5.015** ns 13 tckf clkout fall time (1) ?5.015** ns 14 tckl2iov clkout ? to port out valid (1) ??40** ns 15 tiov2ckh port in valid before clkout ? (1) 0.25 tcy+30* ? ? ns 16 tckh2ioi port in hold after clkout ? (1) 0* ? ? ns 17 tosh2iov osc1 ? (q1 cycle) to port out valid (2) ? ? 100* ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time (2) ?1025** ns 21 tiof port output fall time (2) ?1025** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x tosc. 2: please refer to figure 12-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value 19 note: please refer to figure 12-1 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 77 pic16c5x figure 12-4: reset, watchdog timer, and device reset timer timing - pic16c54/55/56/57 table 12-3: reset, watchdog timer, and device reset timer - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100* ? ? ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (comm) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (comm) 34 tio z i/o hi-impedance from mclr low ? ? 100* ns * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) 30 note 1: please refer to figure 12-1 for load conditions.
pic16c5x ds30453e-page 78 preliminary ? 1997-2013 microchip technology inc. figure 12-5: timer0 clock ti mings - pic16c54/55/56/57 table 12-4: timer0 clock requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40 * n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 note: please refer to figure 12-1 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 79 pic16c5x 13.0 electrical characteristics - pic16cr54a absolute maximum ratings ( ? ) ambient temperature under bias ................................................................................................. .... ?55c to +125c storage temperature ............................................................................................................ ........... ?65c to +150c voltage on v dd with respect to v ss ............................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (1) ...................................................................................................... 0 to +14v voltage on all other pins with respect to v ss ............................................................................?0.6v to (v dd + 0.6v) total power dissipation (2) ............................................................................................................................... 800 mw max. current out of v ss pin ........................................................................................................................... .. 150 ma max. current into v dd pin ........................................................................................................................... ....... 50 ma max. current into an input pin (t0cki only) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 500 ? a input clamp current, i ik (vi < 0 or vi > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????? 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ??????????????????????????????????????????????????????????????? ?????????????????????????????????????????? 20 ma max. output current sunk by any i/o pin ........................................................................................ ................... 25 ma max. output current sourced by any i/o pin ..................................................................................... ................. 20 ma max. output current sourced by a single i/o port (porta or b) .................................................................. ..... 40 ma max. output current sunk by a single i/o port (porta or b) ..................................................................... ....... 50 ma note 1: voltage spikes below vss at the mclr pin, inducing currents greater than 80 ma may cause latch-up. thus, a series resistor of 50 to 100 ? should be used when applying a low level to the mclr pin rather than pulling this pin directly to vss. 2: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453e-page 80 preliminary ? 1997-2013 microchip technology inc. 13.1 dc characteristics: pic16cr54a-04, 10, 20, pic16lcr54a-04 (commercial) pic16cr54a-04i, 10i, 20i, pic16lcr54a-04i (industrial) pic16lcr54a-04 pic16lcr54a-04i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial pic16cr54a-04, 10, 20 pic16cr54a-04i, 10i, 20i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions v dd supply voltage d001 pic16lcr54a 2.0 ? 6.25 v d001 d001a pic16cr54a 2.5 4.5 ? ? 6.25 5.5 v v rc and xt modes hs mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset i dd supply current (2) d005 piclcr54a ? ? 10 ? 20 70 ? a ? a fosc = 32 khz, v dd = 2.0v fosc = 32 khz, v dd = 6.0v d005a pic16cr54a ? ? ? ? ? 2.0 0.8 90 4.8 9.0 3.6 1.8 350 10 20 ma ma ? a ma ma rc (3) and xt modes: f osc = 4.0 mhz, v dd = 6.0v f osc = 4.0 mhz, v dd = 3.0v f osc = 200 khz, v dd = 2.5v hs mode: f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 81 pic16c5x i pd power-down current (2) d006 pic16lcr54a-commercial ? ? ? ? 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 ? a ? a ? a ? a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled d006a pic16cr54a-commercial ? ? ? ? 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 ? a ? a ? a ? a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled d007 pic16lcr54a-industrial ? ? ? ? ? 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 ? a ? a ? a ? a ? a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 4.0v, wdt enabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled d007a pic16cr54a-industrial ? ? ? ? ? 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 ? a ? a ? a ? a ? a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 4.0v, wdt enabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled 13.1 dc characteristics: pic16cr54a-04, 10, 20, pic16lcr54a-04 (commercial) pic16cr54a-04i, 10i, 20i, pic16lcr54a-04i (industrial) pic16lcr54a-04 pic16lcr54a-04i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial pic16cr54a-04, 10, 20 pic16cr54a-04i, 10i, 20i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 82 preliminary ? 1997-2013 microchip technology inc. 13.2 dc characteristics:pic16cr54a-04e, 10e, 20e (extended) pic16cr54a-04e, 10e, 20e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions d001 v dd supply voltage rc, xt and lp modes hs mode 3.25 4.5 ? ? 6.0 5.5 v v d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power- on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) rc (3) and xt modes hs mode hs mode ? ? ? 1.8 4.8 9.0 3.3 10 20 ma ma ma f osc = 4.0 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v d020 i pd power-down current (2) ? ? 5.0 0.8 22 18 ? a ? a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode.the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 83 pic16c5x 13.3 dc characteristics: pic16cr54a-04, 10, 20, pic16lcr54a-04 (commercial) pic16cr54a-04i, 10i, 20i, pic16lcr54a-04i (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic min typ? max units conditions d030 v il input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd v v v v v pin at hi-impedance rc mode only (3) xt, hs and lp modes d040 v ih input high voltage i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 2.0 0.6 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.85 v dd ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v v v v v v v dd = 3.0v to 5.5v (4) full v dd range (4) rc mode only (3) xt, hs and lp modes d050 v hys hysteresis of schmitt trigger inputs 0.15 v dd *? ? v d060 i il input leakage current (1,2) i/o ports mclr mclr t0cki osc1 ?1.0 ?5.0 ? ?3.0 ?3.0 ? ? 0.5 0.5 0.5 +1.0 ? +5.0 +3.0 +3.0 ? a ? a ? a ? a ? a for v dd ? 5.5v: v ss ? v pin ? v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss ? v pin ? v dd v ss ? v pin ? v dd , xt, hs and lp modes d080 v ol output low voltage i/o ports osc2/clkout ? ? ? ? 0.5 0.5 v v i ol = 10 ma, v dd = 6.0v i ol = 1.9 ma, v dd = 6.0v, rc mode only d090 v oh output high voltage (2) i/o ports osc2/clkout v dd ? 0.5 v dd ? 0.5 ? ? ? ? v v i oh = ?4.0 ma, v dd = 6.0v i oh = ?0.8 ma, v dd = 6.0v, rc mode only * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 2: negative current is defined as coming out of the pin. 3: for the rc mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 4: the user may use the better of the two specifications.
pic16c5x ds30453e-page 84 preliminary ? 1997-2013 microchip technology inc. 13.4 dc characteristics: pic16cr54a-04e, 10e, 20e (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions d030 v il input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 vss vss vss vss vss ? ? ? ? ? 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance rc mode only (3) xt, hs and lp modes d040 v ih input high voltage i/o ports i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (4) 4.0v < v dd ? 5.5v (4) v dd > 5.5v rc mode only (3) xt, hs and lp modes d050 v hys hysteresis of schmitt trigger inputs 0.15 v dd *? ? v d060 i il input leakage current (1,2) i/o ports mclr mclr t0cki osc1 ?1.0 ?5.0 ? ?3.0 ?3.0 0.5 ? 0.5 0.5 0.5 +1.0 ? +5.0 +3.0 +3.0 ? a ? a ? a ? a ? a for v dd ? 5.5v: v ss ? v pin ? v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss ? v pin ? v dd v ss ? v pin ? v dd , xt, hs and lp modes d080 v ol output low voltage i/o ports osc2/clkout ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, rc mode only d090 v oh output high voltage (2) i/o ports osc2/clkout v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ?5.4 ma, v dd = 4.5v i oh = ?1.0 ma, v dd = 4.5v, rc mode only * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 2: negative current is defined as coming out of the pin. 3: for the rc mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 4: the user may use the better of the two specifications.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 85 pic16c5x 13.5 timing parameter symbology and load conditions the timing parameter symbols have been created with one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 13-1: load conditions for device timing specifications - pic16cr54a c l = 50 pf for all pins and osc2 for rc modes 0 -15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 c l v ss pin
pic16c5x ds30453e-page 86 preliminary ? 1997-2013 microchip technology inc. 13.6 timing diagrams and specifications figure 13-2: external clo ck timing - pic16cr54a table 13-1: external clock timing requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions f osc external clkin frequency (1) dc ? 4.0 mhz xt osc mode dc ? 4.0 mhz hs osc mode (04) dc ? 10 mhz hs osc mode (10) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4.0 mhz rc osc mode 0.1 ? 4.0 mhz xt osc mode 4.0 ? 4.0 mhz hs osc mode (04) 4.0 ? 10 mhz hs osc mode (10) 4.0 ? 20 mhz hs osc mode (20) 5.0 ? 200 khz lp osc mode * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 1997-2013 microchip technology inc. preliminary ds30453e-page 87 pic16c5x 1t osc external clkin period (1) 250 ? ? ns xt osc mode 250 ? ? ns hs osc mode (04) 100 ? ? ns hs osc mode (10) 50 ? ? ns hs osc mode (20) 5.0 ? ? ? slp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 250 ? 250 ns hs osc mode (04) 100 ? 250 ns hs osc mode (10) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 ? slp osc mode 2 tcy instruction cycle time (2) ?4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 50* ? ? ns xt oscillator 20* ? ? ns hs oscillator 2.0* ? ? ? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 25* ns hs oscillator ? ? 50* ns lp oscillator table 13-1: external clock timing requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x ds30453e-page 88 preliminary ? 1997-2013 microchip technology inc. figure 13-3: clkout and i/o timing - pic16cr54a table 13-2: clkout and i/o timing requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units 10 tosh2ckl osc1 ? to clkout ? (1) ?1530**ns 11 tosh2ckh osc1 ? to clkout ? (1) ?1530**ns 12 tckr clkout rise time (1) ?5.015**ns 13 tckf clkout fall time (1) ?5.015**ns 14 tckl2iov clkout ? to port out valid (1) ??40**ns 15 tiov2ckh port in valid before clkout ? (1) 0.25 tcy+30* ? ? ns 16 tckh2ioi port in hold after clkout ? (1) 0* ? ? ns 17 tosh2iov osc1 ? (q1 cycle) to port out valid (2) ? ? 100* ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time (2) ?1025**ns 21 tiof port output fall time (2) ?1025**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: please refer to figure 13.1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 14 17 20, 21 18 15 11 16 old value new value 19 12 13 note: please refer to figure 13.1 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 89 pic16c5x figure 13-4: reset, watchdog timer, and device reset timer timing - pic16cr54a table 13-3: reset, watchdog timer, and device reset timer - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1.0* ? ? ? sv dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 7.0* 18* 40* ms v dd = 5.0v (comm) 32 t drt device reset timer period 7.0* 18* 30* ms v dd = 5.0v (comm) 34 tio z i/o hi-impedance from mclr low ? ? 1.0* ? s * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) 30 note 1: please refer to figure 13.1 for load conditions.
pic16c5x ds30453e-page 90 preliminary ? 1997-2013 microchip technology inc. figure 13-5: timer0 clo ck timings - pic16cr54a table 13-4: timer0 clock requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40 * n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 note: please refer to figure 13.1 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 91 pic16c5x 14.0 device characterization - pic16c54a the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaran- teed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. ?typical? represents the mean of the distribution at 25c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean ? 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 14-1: typical rc oscillator frequency vs. temperature table 14-1: rc oscillator frequencies c ext r ext average f osc @ 5 v, 25 ? c 20 pf 3.3k 5 mhz ? 27% 5k 3.8 mhz ? 21% 10k 2.2 mhz ? 21% 100k 262 khz ? 31% 100 pf 3.3k 1.6 mhz ? 13% 5k 1.2 mhz ? 13% 10k 684 khz ? 18% 100k 71 khz ? 25% 300 pf 3.3k 660 khz ? 10% 5.0k 484 khz ? 14% 10k 267 khz ? 15% 100k 29 khz ? 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is ? 3 standard deviations from the average value for v dd = 5v. f osc f osc (25 ? c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( ? c) frequency normalized to +25 ? c v dd = 5.5v v dd = 3.5v r ext ?? 10 ? k ? c ext = 100 pf 0.88
pic16c5x ds30453e-page 92 preliminary ? 1997-2013 microchip technology inc. figure 14-2: typical rc osc frequency vs. v dd , cext = 20 pf figure 14-3: typical rc osc frequency vs. v dd , cext = 100 pf 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 93 pic16c5x figure 14-4: typical rc osc frequency vs. v dd , cext = 300 pf figure 14-5: typical ipd vs. v dd , watchdog disabled 800 700 600 500 400 300 200 100 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (khz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( ? a) v dd (volts) t = 25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 94 preliminary ? 1997-2013 microchip technology inc. figure 14-6: maximum ipd vs. v dd , watchdog disabled figure 14-7: typical ipd vs. v dd , watchdog enabled figure 14-8: maximum i pd vs. v dd , watchdog enabled 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ipd ( ? a) v dd (volts) 1 6.5 7.0 10 100 +85c 0c ?40c ?55c +125c +70c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 20 16 12 8 4 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( ? a) v dd (volts) 2 6 10 14 18 t = 25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) +70 ? c 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( ? a) v dd (volts) 6.5 7.0 40 60 +85 ? c ?40 ? c ?55 ? c 10 20 30 50 +125 ? c 0 ? c i pd , with wdt enabled, has two components: the leakage current, which increases with higher temper- ature, and the operating current of the wdt logic, which increases with lower temperature. at ?40 ? c, the latter dominates explaining the apparently anomalous behav- ior. typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 95 pic16c5x figure 14-9: v th (input threshold voltage) of i/o pins vs. v dd figure 14-10: v ih , v il of mclr , t0cki and osc1 (rc mode) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) m i n ( ? 4 0 ? c t o + 8 5 ? c ) 0.80 0.60 5.5 6.0 m a x ( ? 4 0 ? c t o + 8 5 ? c ) t y p ( + 2 5 ? c ) v th (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ? 40 ? c t o + 8 5 ? c ) v i h m ax ( ?4 0 ? c t o + 8 5 ? c ) v i h t y p + 2 5 ? c v i l m i n ( ? 4 0 ? c t o + 8 5 ? c ) v i l m a x ( ? 4 0 ? c t o + 8 5 ? c ) v i h t y p + 2 5 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) note: these input pins have schmitt trigger input buffers.
pic16c5x ds30453e-page 96 preliminary ? 1997-2013 microchip technology inc. figure 14-11: v th (input threshold voltage) of osc1 input (xt, hs, and lp modes) vs. v dd figure 14-12: typical idd vs. frequency (external clock, 25 ? c) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 m a x ( ? 4 0 ? c t o + 8 5 ? c ) m i n ( ? 4 0 ? c t o + 8 5 ? c ) 1.4 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 97 pic16c5x figure 14-13: maximum idd vs. fr equency (external clock, ?40 ? c to +85 ? c) figure 14-14: maximum i dd vs. frequency (e xternal clock ?55 ? c to +125 ? c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 3.5 5.5 6.0 6.5 7.0 2.5 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 98 preliminary ? 1997-2013 microchip technology inc. figure 14-15: wdt timer time-out period vs. v dd (1) figure 14-16: transconductance (gm) of hs oscillator vs. v dd 50 45 40 35 30 25 20 15 10 5 2.03.04.05.06.07.0 v dd (volts) wdt period (ms) max +85 ? c max +70 ? c typ +25 ? c min 0 ? c min ?40 ? c note 1: prescaler set to 1:1. typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 9000 8000 7000 6000 5000 4000 3000 2000 100 0 2.0 3.0 4.0 5.0 6.0 7.0 v dd (volts) gm ( ? a/v) min +85 ? c max ?40 ? c typ +25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 99 pic16c5x figure 14-17: transconductance (gm) of lp oscillator vs. v dd figure 14-18: transconductance (gm) of xt oscillator vs. v dd 45 40 35 30 25 15 10 5 0 v dd (volts) gm ( ? a/v) min +85 ? c max ?40 ? c typ +25 ? c 2.0 3.0 4.0 5.0 6.0 7.0 20 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 2500 2000 1500 1000 500 0 v dd (volts) gm ( ? a/v) min +85 ? c max ?40 ? c typ +25 ? c 2.0 3.0 4.0 5.0 6.0 7.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 100 preliminary ? 1997-2013 microchip technology inc. figure 14-19: porta, b and c i oh vs. v oh , v dd = 3 v figure 14-20: porta, b and c i oh vs. v oh , v dd = 5 v 0 ?5 ?10 ?15 ?20 ?25 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 ? c 3.0 typ +25 ? c max ?40 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 0 ?10 ?20 ?30 ?40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) min +85 ? c max ?40 ? c 4.5 5.0 typ +25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 101 pic16c5x figure 14-21: porta, b and c i ol vs. v ol , v dd = 3 v figure 14-22: porta, b and c i ol vs. v ol , v dd = 5 v 45 40 30 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 25 35 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 102 preliminary ? 1997-2013 microchip technology inc. table 14-2: input capacitance for pic16c54/56 table 14-3: input capacitance for pic16c55/57 pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 ? c. a part-to-part variation of 25% (three standard deviations) should be taken into account. pin typical capacitance (pf) 28l pdip (600 mil) 28l soic ra port 5.2 4.8 rb port 5.6 4.7 rc port 5.0 4.1 mclr 17.0 17.0 osc1 6.6 3.5 osc2/clkout 4.6 3.5 t0cki 4.5 3.5 all capacitance values are typical at 25 ? c. a part-to-part variation of 25% (three standard deviations) should be taken into account.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 103 pic16c5x 15.0 electrical characteristics - pic16c54a absolute maximum ratings (?) ambient temperature under bias................................................................................................. ..... ?55c to +125c storage temperature ............................................................................................................ ........... ?65c to +150c voltage on v dd with respect to v ss ............................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss .......................................................................................................... 0 to +14v voltage on all other pins with respect to v ss ............................................................................?0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... 800 mw max. current out of v ss pin ........................................................................................................................... .. 150 ma max. current into v dd pin ........................................................................................................................... ..... 100 ma max. current into an input pin (t0cki only) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 500 ? a input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ???????????????????????????????????????????????? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ?????????????????????????????????????????? 20 ma max. output current sunk by any i/o pin ........................................................................................ ................... 25 ma max. output current sourced by any i/o pin ..................................................................................... ................. 20 ma max. output current sourced by a single i/o port (porta or b) .................................................................. ..... 50 ma max. output current sunk by a single i/o port (porta or b) ..................................................................... ....... 50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453e-page 104 preliminary ? 1997-2013 microchip technology inc. 15.1 dc characteristics: pic16c54a-04, 10, 20 (commercial) pic16c54a-04i, 10i, 20i (industrial) pic16lc54a-04 (commercial) pic16lc54a-04i (industrial) pic16lc54a-04 pic16lc54a-04i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial pic16c54a-04, 10, 20 pic16c54a-04i, 10i, 20i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions v dd supply voltage d001 pic16lc54a 3.0 2.5 ? ? 6.25 6.25 v v xt and rc modes lp mode d001a pic16c54a 3.0 4.5 ? ? 6.25 5.5 v v rc, xt and lp modes hs mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset i dd supply current (2) d005 pic16lc5x ? ? ? 0.5 11 11 2.5 27 35 ma ? a ? a f osc = 4.0 mhz, v dd = 5.5v, rc (3) and xt modes f osc = 32 khz, v dd = 2.5v, wdt disabled, lp mode, commercial f osc = 32 khz, v dd = 2.5v, wdt disabled, lp mode, industrial d005a pic16c5x ? ? ? ? ? 1.8 2.4 4.5 14 17 2.4 8.0 16 29 37 ma ma ma ? a ? a f osc = 4.0 mhz, v dd = 5.5v, rc (3) and xt modes f osc = 10 mhz, v dd = 5.5v, hs mode f osc = 20 mhz, v dd = 5.5v, hs mode f osc = 32 khz, v dd = 3.0v, wdt disabled, lp mode, commercial f osc = 32 khz, v dd = 3.0v, wdt disabled, lp mode, industrial legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is based on characterization results at 25c. this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 105 pic16c5x i pd power-down current (2) d006 pic16lc5x ? ? ? ? 2.5 0.25 2.5 0.25 12 4.0 14 5.0 ? a ? a ? a ? a v dd = 2.5v, wdt enabled, commercial v dd = 2.5v, wdt disabled, commercial v dd = 2.5v, wdt enabled, industrial v dd = 2.5v, wdt disabled, industrial d006a pic16c5x ? ? ? ? 4.0 0.25 5.0 0.3 12 4.0 14 5.0 ? a ? a ? a ? a v dd = 3.0v, wdt enabled, commercial v dd = 3.0v, wdt disabled, commercial v dd = 3.0v, wdt enabled, industrial v dd = 3.0v, wdt disabled, industrial 15.1 dc characteristics: pic16c54a-04, 10, 20 (commercial) pic16c54a-04i, 10i, 20i (industrial) pic16lc54a-04 (commercial) pic16lc54a-04i (industrial) pic16lc54a-04 pic16lc54a-04i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial pic16c54a-04, 10, 20 pic16c54a-04i, 10i, 20i (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial param no. symbol characteristic/device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is based on characterization results at 25c. this data is for design guidance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 106 preliminary ? 1997-2013 microchip technology inc. 15.2 dc characteristics: pic16c54a-04e, 10e, 20e (extended) pic16lc54a-04e (extended) pic16lc54a-04e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125 ? c for extended pic16c54a-04e, 10e, 20e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions v dd supply voltage d001 pic16lc54a 3.0 2.5 ? ? 6.25 6.25 v v xt and rc modes lp mode d001a pic16c54a 3.5 4.5 ? ? 5.5 5.5 v v rc and xt modes hs mode d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset i dd supply current (2) d010 pic16lc54a ? ? ? ? 0.5 11 11 11 25 27 35 37 ma ? a ? a ? a f osc = 4.0 mhz, v dd = 5.5v, rc (3) and xt modes f osc = 32 khz, v dd = 2.5v, lp mode, commercial f osc = 32 khz, v dd = 2.5v, lp mode, industrial f osc = 32 khz, v dd = 2.5v, lp mode, extended d010a pic16c54a ? ? ? 1.8 4.8 9.0 3.3 10 20 ma ma ma f osc = 4.0 mhz, v dd = 5.5v, rc (3) and xt modes f osc = 10 mhz, v dd = 5.5v, hs mode f osc = 20 mhz, v dd = 5.5v, hs mode legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 107 pic16c5x i pd power-down current (2 ) d020 pic16lc54a ? ? 2.5 0.25 15 7.0 ? a ? a v dd = 2.5v, wdt enabled, extended v dd = 2.5v, wdt disabled, extended d020a pic16c54a ? ? 5.0 0.8 22 18* ? a ? a v dd = 3.5v, wdt enabled v dd = 3.5v, wdt disabled 15.2 dc characteristics: pic16c54a-04e, 10e, 20e (extended) pic16lc54a-04e (extended) pic16lc54a-04e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125 ? c for extended pic16c54a-04e, 10e, 20e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 108 preliminary ? 1997-2013 microchip technology inc. 15.3 dc characteristics: pic16lv54a-02 (commercial) pic16lv54a-02i (industrial) pic16lv54a-02 pic16lv54a-02i ( commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?20 ? c ? t a ? +85 ? c for industrial param no. symbol characteristic min typ? max units conditions d001 v dd supply voltage rc and xt modes 2.0 ? 3.8 v d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) rc (3) and xt modes lp mode, commercial lp mode, industrial ? ? ? 0.5 11 14 ? 27 35 ma ? a ? a f osc = 2.0 mhz, v dd = 3.0v f osc = 32 khz, v dd = 2.5v wdt disabled f osc = 32 khz, v dd = 2.5v wdt disabled d020 i pd power-down current (2,4) commercial commercial industrial industrial ? ? ? ? 2.5 0.25 3.5 0.3 12 4.0 14 5.0 ? a ? a ? a ? a v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr =v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r =v dd /2r ext (ma) with r ext in k ? . 4: the oscillator start-up time can be as much as 8 seconds for xt and lp oscillator selection on wake-up from sleep mode or during initial power-up.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 109 pic16c5x 15.4 dc characteristics: pic16c54a-04, 10, 20, pic16lc54a-04, pic16lv54a-02 (commercial) pic16c54a-04i, 10i, 20i, pic16lc54a-04i, pic16lv54a-02i (industrial) pic16c54a-04e, 10e, 20e, pic16lc54a-04e (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial-pic16lv54a-02i ?40c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions d030 vil input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v pin at hi-impedance rc mode only (3) xt, hs and lp modes d040 vih input high voltage i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 0.2 v dd + 1 2.0 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v v v v v v for all v dd (4) 4.0v < v dd ?? 5.5v (4) rc mode only (3) xt, hs and lp modes d050 v hys hysteresis of schmitt trigger inputs 0.15 v dd *? ? v d060 iil input leakage current (1,2) i/o ports mclr mclr t0cki osc1 -1.0 -5.0 ? -3.0 -3.0 0.5 ? 0.5 0.5 0.5 +1.0 +5.0 +3.0 +3.0 ? ? a ? a ? a ? a ? a for v dd ? 5.5v: v ss ?? v pin ? v dd , pin at hi-impedance v pin = v ss +0.25v v pin = v dd v ss ? v pin ?? v dd v ss ? v pin ? v dd , xt, hs and lp modes d080 vol output low voltage i/o ports osc2/clkout ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, rc mode only voh output high voltage (2) i/o ports osc2/clkout v dd - 0.7 v dd - 0.7 ? ? ? ? v v i oh = -5.4 ma, v dd = 4.5v i oh = -1.0 ma, v dd = 4.5v, rc mode only * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guidance only and is not tested. note 1: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 2: negative current is defined as coming out of the pin. 3: for the rc mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode.
pic16c5x ds30453e-page 110 preliminary ? 1997-2013 microchip technology inc. 15.5 timing parameter symbology and load conditions the timing parameter symbols have been created with one of the following formats: figure 15-1: load conditions for device timing specifications - pic16c54a 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance c l = 50 pf for all pins and osc2 for rc modes 0 -15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 c l v ss pin
? 1997-2013 microchip technology inc. preliminary ds30453e-page 111 pic16c5x 15.6 timing diagrams and specifications figure 15-2: external clock timing - pic16c54a table 15-1: external clock timing requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial - pic16lv54a-02i ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions f osc external clkin fre- quency (1) dc ? 4.0 mhz xt osc mode dc ? 2.0 mhz xt osc mode (pic16lv54a) dc ? 4.0 mhz hs osc mode (04) dc ? 10 mhz hs osc mode (10) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4.0 mhz rc osc mode dc ? 2.0 mhz rc osc mode (pic16lv54a) 0.1 ? 4.0 mhz xt osc mode 0.1 ? 2.0 mhz xt osc mode (pic16lv54a) 4.0 ? 4.0 mhz hs osc mode (04) 4.0 ? 10 mhz hs osc mode (10) 4.0 ? 20 mhz hs osc mode (20) 5.0 ? 200 khz lp osc mode * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
pic16c5x ds30453e-page 112 preliminary ? 1997-2013 microchip technology inc. 1t osc external clkin period (1) 250 ? ? ns xt osc mode 500 ? ? ns xt osc mode (pic16lv54a) 250 ? ? ns hs osc mode (04) 100 ? ? ns hs osc mode (10) 50 ? ? ns hs osc mode (20) 5.0 ? ? ? slp osc mode oscillator period (1) 250 ? ? ns rc osc mode 500 ? ? ns rc osc mode (pic16lv54a) 250 ? 10,000 ns xt osc mode 500 ? ? ns xt osc mode (pic16lv54a) 250 ? 250 ns hs osc mode (04) 100 ? 250 ns hs osc mode (10) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 ? slp osc mode 2 tcy instruction cycle time (2) ?4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 85* ? ? ns xt oscillator 20* ? ? ns hs oscillator 2.0* ? ? ? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 25* ns hs oscillator ? ? 50* ns lp oscillator table 15-1: external clock timing requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial - pic16lv54a-02i ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 113 pic16c5x figure 15-3: clkout and i/o timing - pic16c54a table 15-2: clkout and i/o timing requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial - pic16lv54a-02i ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units 10 tosh2ckl osc1 ? to clkout ? (1) ?1530**ns 11 tosh2ckh osc1 ? to clkout ? (1) ?1530**ns 12 tckr clkout rise time (1) ?5.015**ns 13 tckf clkout fall time (1) ?5.015**ns 14 tckl2iov clkout ? to port out valid (1) ??40**ns 15 tiov2ckh port in valid before clkout ? (1) 0.25 tcy+30* ? ? ns 16 tckh2ioi port in hold after clkout ? (1) 0* ? ? ns 17 tosh2iov osc1 ? (q1 cycle) to port out valid (2) ? ? 100* ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time (2) ?1025**ns 21 tiof port output fall time (2) ?1025**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. ? data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guid- ance only and is not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: please refer to figure 15-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value 19 note: please refer to figure 15-1 for load conditions.
pic16c5x ds30453e-page 114 preliminary ? 1997-2013 microchip technology inc. figure 15-4: reset, watchdog timer, and device reset timer timing - pic16c54a table 15-3: reset, watchdog timer, and device reset timer - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial - pic16lv54a-02i ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100* 1 ? ? ? ? ns ? s v dd = 5.0v v dd = 5.0v (pic16lv54a only) 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (comm) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (comm) 34 tio z i/o hi-impedance from mclr low ? ? ? ? 100* 1 ? s ns ? (pic16lv54a only) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) 30 note 1: please refer to figure 15-1 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 115 pic16c5x figure 15-5: timer0 clo ck timings - pic16c54a table 15-4: timer0 clock requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?20 ? c ? t a ? +85 ? c for industrial - pic16lv54a-02i ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40 * n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 note: please refer to figure 15-1 for load conditions.
pic16c5x ds30453e-page 116 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 117 pic16c5x 16.0 device characterization - pic16c54a the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaran- teed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. ?typical? represents the mean of the distribution at 25c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean ? 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 16-1: typical rc oscillator frequency vs. temperature table 16-1: rc oscillator frequencies c ext r ext average fosc @ 5 v, 25 ? c 20 pf 3.3k 5 mhz ? 27% 5k 3.8 mhz ? 21% 10k 2.2 mhz ? 21% 100k 262 khz ? 31% 100 pf 3.3k 1.6 mhz ? 13% 5k 1.2 mhz ? 13% 10k 684 khz ? 18% 100k 71 khz ? 25% 300 pf 3.3k 660 khz ? 10% 5.0k 484 khz ? 14% 10k 267 khz ? 15% 100k 29 khz ? 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is ? 3 standard deviation from average value for v dd = 5v. fosc fosc (25 ? c) 1.10 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0202530405070 t( ? c) frequency normalized to +25 ? c v dd = 5.5v v dd = 3.5v r ext ? 10 kw c ext = 100 pf 0.88 1.08 60 10
pic16c5x ds30453e-page 118 preliminary ? 1997-2013 microchip technology inc. figure 16-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f, 2 5 ? c figure 16-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f, 2 5 ? c 3.5 4.5 5.5 2.5 f osc (mhz) r=3.3k r=5k r=10k r=100k 4.0 5.0 6.0 v dd (volts) 6 5 4 3 2 1 0 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) r=3.3k r=5k r=10k r=100k 3.5 4.5 2.5 f osc (mhz) 4.0 5.0 6.0 v dd (volts) 6 5 4 3 2 1 0 3.0 5.5 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 119 pic16c5x figure 16-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f, 2 5 ? c f osc (khz) 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 r=3.3k r=5k r=10k r=100k v dd (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 120 preliminary ? 1997-2013 microchip technology inc. figure 16-5: typical i pd vs. v dd , watchdog disabled (25 ? c) figure 16-6: typical i pd vs . v dd , watchdog enabled (25 ? c) 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0 5.5 6.0 i pd ( ? a) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 25.00 20.00 15.00 10.00 5.00 0.00 2.5 3 3.5 4.5 5.5 456 v dd (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 121 pic16c5x figure 16-7: v th (input threshold voltage) of i/o pins - v dd figure 16-8: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) m i n ( ? 4 0 ? c t o + 8 5 ? c ) 0.8 0.6 5.5 6.0 m a x ( ? 4 0 ? c t o + 8 5 ? c ) t y p ( + 2 5 ? c ) v th (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 m a x ( ? 4 0 ? c t o + 8 5 ? c ) m i n ( ? 4 0 ? c t o + 8 5 ? c ) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 122 preliminary ? 1997-2013 microchip technology inc. figure 16-9: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ?4 0 ? c t o + 8 5 ? c ) v i h m ax ( ? 4 0 ? c t o + 85 ? c ) v i h t y p + 2 5 ? c v i l m i n ( ? 4 0 ? c t o + 8 5 ? c ) v i l m a x ( ? 4 0 ? c t o + 8 5 ? c ) v i l t y p + 2 5 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) note: these input pins have schmitt trigger input buffers.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 123 pic16c5x figure 16-10: typical i dd vs. frequency (wdt disabled, rc mode @ 20 p f, 2 5 ? c) figure 16-11: maximum i dd vs. frequency (wdt disabled, rc mode @ 20 p f, ?40 ? c to +85 ? c) 10000 1000 100 10 0.1 1 10 i dd ( ? a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 10000 1000 100 10 110 i dd ( ? a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 0.1 freq (mhz) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 124 preliminary ? 1997-2013 microchip technology inc. figure 16-12: typical i dd vs. frequency (wdt disabled, rc mode @ 100 p f, 2 5 ? c) figure 16-13: maximum i dd vs. frequency (wdt disabled, rc mode @ 100 p f, ?40 ? c to +85 ? c) 10000 1000 100 10 0.01 110 i dd ( ? a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) 0.1 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 10000 1000 100 10 0.01 1 10 i dd ( ? a) freq (mhz) 0.1 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 125 pic16c5x figure 16-14: typical i dd vs. frequency (wdt disabled, rc mode @ 300 p f, 2 5 ? c) figure 16-15: maximum i dd vs. frequency (wdt disabled, rc mode @ 300 p f, ?40 ? c to +85 ? c) 10000 1000 100 10 0.01 0.1 1 i dd ( ? a) freq (mhz) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 1000 100 10 0.01 0.1 i dd ( ? a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) 1 10000 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 126 preliminary ? 1997-2013 microchip technology inc. figure 16-16: wdt timer time-out period vs. v dd (1) figure 16-17: transconductance (gm) of hs oscillator vs. v dd 50 45 40 35 30 25 20 15 10 5 2.0 3.0 4.0 5.0 6.0 7.0 v dd (volts) wdt period (ms) max +85 ? c max +70 ? c typ +25 ? c min 0 ? c min ?40 ? c note 1: prescaler set to 1:1. typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 9000 8000 7000 5000 4000 100 0 v dd (volts) gm ( ? a/w) min +85 ? c max ?40 ? c typ +25 ? c 2.0 3.0 4.0 5.0 6.0 7.0 6000 3000 2000 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 127 pic16c5x figure 16-18: transconductance (gm) of lp oscillator vs. v dd figure 16-19: transconductance (gm) of xt oscillator vs. v dd 45 40 35 30 25 20 15 10 5 0 v dd (volts) gm ( ? a/v) min +85 ? c max ?40 ? c typ +25 ? c 2.0 3.0 4.0 5.0 6.0 7.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 2500 2000 1500 1000 500 0 v dd (volts) gm ( ? a/v) min +85 ? c max ?40 ? c typ +25 ? c 2.0 3.0 4.0 5.0 6.0 7.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 128 preliminary ? 1997-2013 microchip technology inc. figure 16-20: porta, b and c i oh vs. v oh , v dd = 3v figure 16-21: porta, b and c i oh vs. v oh , v dd = 5v 0 ?5 ?10 ?15 ?20 ?25 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 ? c 3.0 typ +25 ? c max ?40 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 0 ?10 ?20 ?30 ?40 1.52.0 2.53.0 3.54.0 v oh (volts) i oh (ma) min +85 ? c max ?40 ? c 4.5 5.0 typ +25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 129 pic16c5x figure 16-22: porta, b and c i ol vs. v ol , v dd = 3v table 16-2: input capacitance for pic16c54a/c58a figure 16-23: porta, b and c i ol vs. v ol , v dd = 5v pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 ? c. a part-to-part variation of ? 25% (three standard deviations) should be taken into account. 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 130 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 131 pic16c5x 17.0 electrical characteristics - pic16lc54a absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... ?55c to +125c storage temperature ............................................................................................................ ................. ?65c to +150c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss ................................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ?0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw max. current out of v ss pin ........................................................................................................................... ........150 ma max. current into v dd pin ........................................................................................................................... ...........100 ma max. current into an input pin (t0cki only) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????? 500 ? a input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? ? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................20 ma max. output current sourced by a single i/o (port a, b or c) .................................................................. ...............50 ma max. output current sunk by a single i/o (port a, b or c) ...................................................................... .................50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453e-page 132 preliminary ? 1997-2013 microchip technology inc. figure 17-1: pic16c54c/55a/56a/57c/58 b-04, 20 voltage-frequency graph, 0 ? c ? t a ? +70 ? c (commercial temps) figure 17-2: pic16c54c/55a/56a/57c/58 b-04, 20 voltage-frequency graph, -40 ? c ? t a ? 0 ? c, +70 ? c ? t a ? +125 ? c (outside of commercial temps) 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 133 pic16c5x figure 17-3: pic16lc54c/55a/56a/57c /58b voltage-frequency graph, 0 ? c ? t a ? +85 ? c figure 17-4: pic16lc54c/55a/56a/57c /58b voltage-frequency graph, -40 ? c ? t a ? 0 ? c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 2.7
pic16c5x ds30453e-page 134 preliminary ? 1997-2013 microchip technology inc. 17.1 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04, 20 (commercial, industrial) pic16lc54c/lc55a/lc56a/lc57c/lc58b-04 (commercial, industrial) pic16cr54c/cr56a/cr57c/cr58b-04, 20 (commercial, industrial) pic16lcr54c/lcr56a/lcr57c/lcr58b-04 (commercial, industrial) pic16lc5x pic16lcr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial pic16c5x pic16cr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial param no. symbol characteristic/device min typ? max units conditions v dd supply voltage d001 pic16lc5x 2.5 2.7 2.5 ? ? ? 5.5 5.5 5.5 v v v ?40 ? c ?? t a ?? + 85 ? c, 16lcr5x ?40 ? c ?? t a ? 0 ? c, 16lc5x 0 ? c ?? t a ?? + 85 ? c 16lc5x d001a pic16c5x 3.0 4.5 ? ? 5.5 5.5 v v rc, xt, lp and hs mode from 0 - 10 mhz from 10 - 20 mhz d002 v dr ram data retention volt- age (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 ? c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = vdd, mclr = vdd; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 135 pic16c5x i dd supply current (2,3) d010 pic16lc5x ? ? ? 0.5 11 14 2.4 27 35 ma ? a ? a f osc = 4.0 mhz, v dd = 5.5v, xt and rc modes f osc = 32 khz, v dd = 2.5v, lp mode, commercial f osc = 32 khz, v dd = 2.5v, lp mode, industrial d010a pic16c5x ? ? ? ? ? 1.8 2.6 4.5 14 17 2.4 3.6* 16 32 40 ma ma ma ? a ? a f osc = 4 mhz, v dd = 5.5v, xt and rc modes f osc = 10 mhz, v dd = 3.0v, hs mode f osc = 20 mhz, v dd = 5.5v, hs mode f osc = 32 khz, v dd = 3.0v, lp mode, commercial f osc = 32 khz, v dd = 3.0v, lp mode, industrial 17.1 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04, 20 (commercial, industrial) pic16lc54c/lc55a/lc56a/lc57c/lc58b-04 (commercial, industrial) pic16cr54c/cr56a/cr57c/cr58b-04, 20 (commercial, industrial) pic16lcr54c/lcr56a/lcr57c/lcr58b-04 (commercial, industrial) pic16lc5x pic16lcr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial pic16c5x pic16cr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial param no. symbol characteristic/device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 ? c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = vdd, mclr = vdd; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 136 preliminary ? 1997-2013 microchip technology inc. i pd power-down current (2) d020 pic16lc5x ? ? ? ? 0.25 0.25 1 1.25 2 3 5 8 ? a ? a ? a ? a v dd = 2.5v, wdt disabled, commercial v dd = 2.5v, wdt disabled, industrial v dd = 2.5v, wdt enabled, commercial v dd = 2.5v, wdt enabled, industrial d020a pic16c5x ? ? ? ? ? ? ? ? 0.25 0.25 1.8 2.0 4 4 9.8 12 4.0 5.0 7.0* 8.0* 12* 14* 27* 30* ? a ? a ? a ? a ? a ? a ? a ? a v dd = 3.0v, wdt disabled, commercial v dd = 3.0v, wdt disabled, industrial v dd = 5.5v, wdt disabled, commercial v dd = 5.5v, wdt disabled, industrial v dd = 3.0v, wdt enabled, commercial v dd = 3.0v, wdt enabled, industrial v dd = 5.5v, wdt enabled, commercial v dd = 5.5v, wdt enabled, industrial 17.1 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04, 20 (commercial, industrial) pic16lc54c/lc55a/lc56a/lc57c/lc58b-04 (commercial, industrial) pic16cr54c/cr56a/cr57c/cr58b-04, 20 (commercial, industrial) pic16lcr54c/lcr56a/lcr57c/lcr58b-04 (commercial, industrial) pic16lc5x pic16lcr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial pic16c5x pic16cr5x (commercial, industrial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial param no. symbol characteristic/device min typ? max units conditions legend: rows with standard voltage device data only are shaded for improved readability. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 ? c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = vdd, mclr = vdd; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
? 1997-2013 microchip technology inc. preliminary ds30453e-page 137 pic16c5x 17.2 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04e, 20e (extended) pic16cr54c/cr56a/cr57c/cr58b-04e, 20e (extended) pic16c54c/c55a/c56a/c57c/c58b-04e, 20e pic16cr54c/cr56a/cr57c/cr58b-04e, 20e (extended) standard operating conditions (unless otherwise specified) operating temperature ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions d001 v dd supply voltage 3.0 4.5 ? ? 5.5 5.5 v v rc, xt, lp, and hs mode from 0 - 10 mhz from 10 - 20 mhz d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (2) xt and rc (3) modes hs mode ? ? 1.8 9.0 3.3 20 ma ma f osc = 4.0 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v d020 i pd power-down current (2) ? ? ? ? ? ? 0.3 10 12 4.8 18 26 17 50* 60* 31* 68* 90* ? a ? a ? a ? a ? a ? a v dd = 3.0v, wdt disabled v dd = 4.5v, wdt disabled v dd = 5.5v, wdt disabled v dd = 3.0v, wdt enabled v dd = 4.5v, wdt enabled v dd = 5.5v, wdt enabled * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 ? c, unless otherwise stated. these parameters are for design guidance only, and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/ disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type. 3: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? .
pic16c5x ds30453e-page 138 preliminary ? 1997-2013 microchip technology inc. 17.3 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04, 20 (commercial, industrial, extended) pic16lc54c/lc55a/lc56a/lc57c/lc58b-04 (commercial, industrial) pic16cr54c/cr56a/cr57c/cr58b-04, 20 (commercial, industrial, extended) pic16lcr54c/lcr56a/lcr57c/lcr5 8b-04 (commercial, industrial ) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions d030 v il input low voltage i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ss v ss v ss v ss v ss v ss ? ? ? ? ? ? 0.8 v 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v v 4.5v ? 1997-2013 microchip technology inc. preliminary ds30453e-page 139 pic16c5x 17.4 timing parameter symbology and load conditions the timing parameter symbols have been created with one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 17-5: load conditions for device timing specifications - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b-04, 20 c l = 50 pf for all pins and osc2 for rc mode 0 -15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 c l v ss pin
pic16c5x ds30453e-page 140 preliminary ? 1997-2013 microchip technology inc. 17.5 timing diagrams and specifications figure 17-6: external cl ock timing - pic16c5x, pic16cr5x table 17-1: external clock timing re quirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions f osc external clkin frequency (1) dc ? 4.0 mhz xt osc mode dc ? 4.0 mhz hs osc mode (04) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4.0 mhz rc osc mode 0.45 ? 4.0 mhz xt osc mode 4.0 ? 4.0 mhz hs osc mode (04) 4.0 ? 20 mhz hs osc mode (20) 5.0 ? 200 khz lp osc mode 1t osc external clkin period (1) 250 ? ? ns xt osc mode 250 ? ? ns hs osc mode (04) 50 ? ? ns hs osc mode (20) 5.0 ? ? ? slp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 2,200 ns xt osc mode 250 ? 250 ns hs osc mode (04) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 ? slp osc mode * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: all specified values are based on characterization data fo r that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 1997-2013 microchip technology inc. preliminary ds30453e-page 141 pic16c5x 2 tcy instruction cycle time (2) ?4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 50* ? ? ns xt oscillator 20* ? ? ns hs oscillator 2.0* ? ? ? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 25* ns hs oscillator ? ? 50* ns lp oscillator table 17-1: external clock timing requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x ds30453e-page 142 preliminary ? 1997-2013 microchip technology inc. figure 17-7: clkout and i/o timing - pic16c5x, pic16cr5x table 17-2: clkout and i/o timing requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70 ? c for commercial ?40 ? c ? t a ? +85 ? c for industrial ?40 ? c ? t a ? +125 ? c for extended param no. symbol characteristic min typ? max units 10 tosh2ckl osc1 ? to clkout ? (1) ? 15 30** ns 11 tosh2ckh osc1 ? to clkout ? (1) ? 15 30** ns 12 tckr clkout rise time (1) ? 5.0 15** ns 13 tckf clkout fall time (1) ? 5.0 15** ns 14 tckl2iov clkout ? to port out valid (1) ? ? 40** ns 15 tiov2ckh port in valid before clkout ? (1) 0.25 tcy+30* ? ? ns 16 tckh2ioi port in hold after clkout ? (1) 0* ? ? ns 17 tosh2iov osc1 ? (q1 cycle) to port out valid (2) ? ? 100* ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time (2) ? 10 25** ns 21 tiof port output fall time (2) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: refer to figure 17-5 for load conditions . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value 19 note: refer to figure 17-5 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 143 pic16c5x figure 17-8: reset, watchdog timer, and device reset timer timing - pic16c5x, pic16cr5x table 17-3: reset, watchdog timer, and device reset timer - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1000* ? ? ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (comm) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (comm) 34 tio z i/o hi-impedance from mclr low 100* 300* 1000* ns * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) 30 note 1: please refer to figure 17-5 for load conditions.
pic16c5x ds30453e-page 144 preliminary ? 1997-2013 microchip technology inc. figure 17-9: timer0 clock ti mings - pic16c5x, pic16cr5x table 17-4: timer0 clock requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial ?40c ? t a ? +85c for industrial ?40c ? t a ? +125c for extended param no. symbol characteristic min typ? max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40 * n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guid- ance only and are not tested. t0cki 40 41 42 note: please refer to figure 17-5 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 145 pic16c5x 18.0 device characterization - pic16lc54a the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaran- teed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. ?typical? represents the mean of the distribution at 25c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean ? 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 18-1: typical rc oscillator frequency vs . temperature table 18-1: rc oscillator frequencies c ext r ext average fosc @ 5v, 25 ? c 20 pf 3.3k 5 mhz 27% 5k 3.8 mhz 21% 10k 2.2 mhz 21% 100k 262 khz 31% 100 pf 3.3k 1.63 mhz 13% 5k 1.2 mhz 13% 10k 684 khz 18% 100k 71 khz 25% 300 pf 3.3k 660 khz 10% 5.0k 484 khz 14% 10k 267 khz 15% 100k 29 khz 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard devia tion from average value for v dd = 5v. f osc f osc (25 ? c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( ? c) frequency normalized to +25 ? c v dd = 5.5v v dd = 3.5v r ext ? 10 kw c ext = 100 pf 0.88
pic16c5x ds30453e-page 146 preliminary ? 1997-2013 microchip technology inc. figure 18-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f, 2 5 ? c figure 18-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f, 2 5 ? c v dd (volts) r=100k r=10k r=3.3k 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 r=5k 6 5 4 2 0 1 3 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 6 v dd (volts) 1.8 1.6 0.6 0 1.0 0.2 r=100k r=10k r=5k r=3.3k f osc (mhz) 1.4 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 147 pic16c5x figure 18-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f, 2 5 ? c figure 18-5: typical i pd vs. v dd , watchdog disabled (25 ? c) v dd (volts) f osc (khz) 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 r=100k r=10k r=5k r=3.3k 600 500 400 200 0 300 100 700 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) v dd (volts) i pd (ua) 25 20 15 5 0 10 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 148 preliminary ? 1997-2013 microchip technology inc. figure 18-6: typical i pd vs. v dd , watchdog enabled (25 ? c) figure 18-7: typical i pd vs. v dd , watchdog enabled ( ? 40c, 85c) v dd (volts) i pd (ua) 25 20 15 0 2.5 3.0 4.5 5.5 4.0 5.0 6.0 10 5.0 3.5 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) v dd (volts) i pd (ua) 35 15 5.0 0 10 ( - 4 0 ? c ) ( + 8 5 ? c ) 20 25 30 2.5 3.0 4.5 5.5 4.0 5.0 6.0 3.5 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 149 pic16c5x figure 18-8: v th (input threshold trip point voltage) of i/o pins vs. v dd figure 18-9: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.8 0.6 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ?4 0 ? c t o + 8 5 ? c ) v i h m ax ( ? 4 0 ? c t o + 85 ? c ) v i h t y p + 2 5 ? c v i l m i n ( ? 4 0 ? c t o + 8 5 ? c ) v i l m a x ( ? 4 0 ? c t o + 8 5 ? c ) v i l t y p + 2 5 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) note: these input pins have schmitt trigger input buffers.
pic16c5x ds30453e-page 150 preliminary ? 1997-2013 microchip technology inc. figure 18-10: v th (input threshold trip point voltage) of osc1 input (in xt, hs and lp modes) vs. v dd figure 18-11: typical i dd vs. frequency (wdt disabled, rc mode @ 20 p f, 2 5 ? c) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) typical i dd vs freq(rc mode @ 20pf/25c) 10 100 1000 10000 0.1 1 10 f req (mhz) i dd ( ? a) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 5.5v 4.5v 3.5v 2.5v
? 1997-2013 microchip technology inc. preliminary ds30453e-page 151 pic16c5x figure 18-12: typical i dd vs. frequency (wdt disabled, rc mode @ 100 p f, 2 5 ? c) figure 18-13: typical i dd vs. frequency (wdt disabled, rc mode @ 300 p f, 2 5 ? c) typical i dd vs freq(rc mode @ 100 pf/25c) 10 100 1000 10000 0.1 1 10 f req (mhz) i dd ( ? a) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 5.5v 4.5v 3.5v 2.5v typical i dd vs f req (rc mode @ 300 pf/25c) 10 1000 10000 0.01 0.1 1 f req (mhz) i dd ( ? a) 100 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 5.5v 4.5v 3.5v 2.5v
pic16c5x ds30453e-page 152 preliminary ? 1997-2013 microchip technology inc. figure 18-14: wdt timer time-out period vs. v dd (1) figure 18-15: porta, b and c i oh vs. v oh , v dd = 3 v 50 45 40 35 30 25 20 15 10 5.0 2.0 3.0 4.0 5.0 6.0 7.0 v dd (volts) wdt period (ms) typ +125 ? c typ +85 ? c typ +25 ? c typ ?40 ? c note 1: prescaler set to 1:1. typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 0 ?5 ?10 ?20 ?25 0 0.5 1.0 2.0 2.5 v oh (volts) i oh (ma) min +85 ? c 3.0 typ +25 ? c max ?40 ? c ?15 1.5 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 153 pic16c5x figure 18-16: porta, b and c i oh vs. v oh , v dd = 5 v figure 18-17: porta, b and c i ol vs. v ol , v dd = 3 v 0 ?20 ?30 ?40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) typ ?40 ? c 4.5 5.0 typ +85 ? c typ +125 ? c typ +25 ? c ?10 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 45 40 35 30 25 20 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 15 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 154 preliminary ? 1997-2013 microchip technology inc. figure 18-18: porta, b and c i ol vs. v ol , v dd = 5 v table 18-2: input capacitance pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 ? c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 155 pic16c5x 19.0 electrical characteristics - pic16lc54c 40mhz absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... ?55c to +125c storage temperature ............................................................................................................ ................. ?65c to +150c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss ................................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ?0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw max. current out of v ss pin ........................................................................................................................... ........150 ma max. current into v dd pin ........................................................................................................................... ...........100 ma max. current into an input pin (t0cki only) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????? 500 ? a input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? ? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................20 ma max. output current sourced by a single i/o (port a, b or c) .................................................................. ...............50 ma max. output current sunk by a single i/o (port a, b or c) ...................................................................... .................50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453e-page 156 preliminary ? 1997-2013 microchip technology inc. figure 19-1: pic16c54c/c55a/c56a/c57c /c58b-40 voltage-frequency graph, 0 ? c ? t a ? +70 ? c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 3: operation between 20 to 40 mhz requires the following: ?v dd between 4.5v. and 5.5v ? osc1 externally driven ? osc2 not connected ?hs mode ? commercial temperatures devices qualified for 40 mhz operation have -40 designation (ex: pic16c54c-40/p). 4: for operation between dc and 20 mhz, see section 17.1. 40
? 1997-2013 microchip technology inc. preliminary ds30453e-page 157 pic16c5x 19.1 dc characteristics:pic16c54c/c55a/c56a/c57c/c58b-40 (commercial) (1) pic16c54c/c55a/c56a/c57c/c58b-40 (commercial) standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial param no. symbol characteristic min typ? max units conditions d001 v dd supply voltage 4.5 ? 5.5 v hs mode from 20 - 40 mhz d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 5.1 for details on power-on reset d004 s vdd v dd rise rate to ensure power- on reset 0.05* ? ? v/ms see section 5.1 for details on power-on reset d010 i dd supply current (3) ? ? 5.2 6.8 12.3 16 ma ma f osc = 40 mhz, v dd = 4.5v, hs mode f osc = 40 mhz, v dd = 5.5v, hs mode d020 i pd power-down current (3) ? ? 1.8 9.8 7.0 27* ? a ? a v dd = 5.5v, wdt disabled, commercial v dd = 5.5v, wdt enabled, commercial * these parameters are characterized but not tested. ? data in the typical (?typ?) column is based on characterization results at 25c. this data is for design guidance only and is not tested. note 1: device operation between 20 mhz to 40 mhz requires the following: v dd between 4.5v to 5.5v, osc1 pin externally driven, osc2 pin not connected, hs oscillator mode and commercial temperatures. for operation between dc and 20 mhz, see section 19.1. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus load- ing, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/dis- abled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. the power-down current in sleep mode does not depend on the oscillator type.
pic16c5x ds30453e-page 158 preliminary ? 1997-2013 microchip technology inc. 19.2 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-40 (commercial) (1) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70 ? c for commercial param no. symbol characteristic min typ? max units conditions d030 v il input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 v ss v ss v ss v ss ? ? ? ? 0.8 0.15 v dd 0.15 v dd 0.2 v dd v v v v 4.5v ? 1997-2013 microchip technology inc. preliminary ds30453e-page 159 pic16c5x 19.3 timing parameter symbology and load conditions the timing parameter symbols have been created with one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 19-2: load conditions for device timing specifications - pic16c54c/c55a/c56a/c57c/c58b-40 c l = 50 pf for all pins except osc2 0 pf for osc2 in hs mode for operation between 20 mhz to 40 mhz c l v ss pin
pic16c5x ds30453e-page 160 preliminary ? 1997-2013 microchip technology inc. 19.4 timing diagrams and specifications figure 19-3: external clock timing - pic16c5x-40 table 19-1: external clock timing requirements - pic16c5x-40 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 ? c ? t a ? +70 ? c for commercial param no. symbol characteristic min typ? max units conditions f osc external clkin frequency (1) 20 ? 40 mhz hs osc mode 1t osc external clkin period (1) 25 ? ? ns hs osc mode 2 tcy instruction cycle time (2) ?4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 6.0* ? ? ns hs oscillator 4 tosr, tosf clock in (osc1) rise or fall time ? ? 6.5* ns hs oscillator * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: all specified values are based on characterization data fo r that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 1997-2013 microchip technology inc. preliminary ds30453e-page 161 pic16c5x figure 19-4: clkout and i/o timing - pic16c5x-40 table 19-2: clkout and i/o timing requirements - pic16c5x-40 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70 ? c for commercial param no. symbol characteristic min typ? max units 10 tosh2ckl osc1 ? to clkout ? (1,2) ? 15 30** ns 11 tosh2ckh osc1 ? to clkout ? (1,2) ? 15 30** ns 12 tckr clkout rise time (1,2) ? 5.0 15** ns 13 tckf clkout fall time (1,2) ? 5.0 15** ns 14 tckl2iov clkout ? to port out valid (1,2) ? ? 40** ns 15 tiov2ckh port in valid before clkout ? (1,2) 0.25 tcy+30* ? ? ns 16 tckh2ioi port in hold after clkout ? (1,2) 0* ? ? ns 17 tosh2iov osc1 ? (q1 cycle) to port out valid (2) ??100ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) tbd ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) tbd ? ? ns 20 tior port output rise time (2) ? 10 25** ns 21 tiof port output fall time (2) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: refer to figure 19-2 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value . 19 note: refer to figure 19-2 for load conditions.
pic16c5x ds30453e-page 162 preliminary ? 1997-2013 microchip technology inc. figure 19-5: reset, watchdog timer, and device reset timer timing - pic16c5x-40 table 19-3: reset, watchdog timer, and device reset timer - pic16c5x-40 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c (commercial) operating voltage v dd range is described in section 19.1. param no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1000* ? ? ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (comm) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (comm) 34 tio z i/o hi-impedance from mclr low 100* 300* 1000* ns * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: please refer to figure 19-2 for load conditions.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 163 pic16c5x figure 19-6: timer0 clo ck timings - pic16c5x-40 table 19-4: timer0 clock requirements pic16c5x-40 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0c ? t a ? +70c for commercial param no. symbol characteristic min typ? max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ? ? ns - with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40 * n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 note: refer to figure 19-2 for load conditions.
pic16c5x ds30453e-page 164 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page 165 pic16c5x 20.0 device characterization - pic16lc54c 40mhz the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaran- teed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. ?typical? represents the mean of the distribution at 25c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean ? 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 20-1: typical i pd vs. v dd , watchdog disabled (25 ? c) v dd (volts) i pd (ua) 25 20 15 5.0 0 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 10 4.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 166 preliminary ? 1997-2013 microchip technology inc. figure 20-2: typical i pd vs. v dd , watchdog enabled (25 ? c) figure 20-3: typical i pd vs. v dd , watchdog enabled ( ? 40c, 85c) v dd (volts) i pd (ua) 25 20 15 0 2.5 3.0 4.5 5.5 4.0 5.0 6.0 10 5.0 3.5 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) v dd (volts) i pd (ua) 35 15 5.0 0 2.5 3.0 3.5 4.5 5.5 4.0 5.0 6.0 10 ( - 4 0 ? c ) ( + 8 5 ? c ) 20 25 30 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 167 pic16c5x figure 20-4: v th (input threshold trip point voltage) of i/o pins vs. v dd figure 20-5: v th (input threshold trip point voltage) of osc1 input (hs mode) vs. v dd 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.8 0.6 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 ? c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 168 preliminary ? 1997-2013 microchip technology inc. figure 20-6: typical i dd vs. v dd (40 mhz, wdt disabled, hs mode, 70 ? c) 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 i dd (ma) v dd (volts) typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 169 pic16c5x figure 20-7: wdt timer time-out period vs. v dd (1) table 20-1: input capacitance figure 20-8: i oh vs. v oh , v dd = 5 v pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 ? c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 50 45 40 35 30 25 20 15 10 5.0 2.0 3.0 4.0 5.0 6.0 7.0 v dd (volts) wdt period (ms) typ +125 ? c typ +85 ? c typ +25 ? c typ ?40 ? c note 1: prescaler set to 1:1. typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c) 0 ?10 ?20 ?30 ?40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) typ ?40 ? c 4.5 5.0 typ +85 ? c typ +125 ? c typ +25 ? c typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
pic16c5x ds30453e-page 170 preliminary ? 1997-2013 microchip technology inc. figure 20-9: i ol vs. v ol , v dd = 5 v 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 ? c max ?40 ? c typ +25 ? c 3.0 typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3s (-40c to 125c)
? 1997-2013 microchip technology inc. preliminary ds30453e-page 171 pic16c5x 21.0 packaging information 21.1 package marketing information xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn 18-lead pdip 28-lead skinny pdip (.300") yywwnnn pic16c56a 0023cba example example -04i/sp456 0023cba pic16c55a yywwnnn 28-lead pdip (.600") -04/p126 0042cda example pic16c55a xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx 18-lead soic xxxxxxxxxxxx yywwnnn 28-lead soic yywwnnn xxxxxxxxxxxxxxxxxxxx 20-lead ssop yywwnnn xxxxxxxxxxx example pic16c54c 0018cdk -04/s0218 example 0015cbk pic16c57c example -04/ss218 0020cbp pic16c54c 28-lead ssop xxxxxxxxxxxx example 0025cbk pic16c57c -04/ss123 xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx -04/so xxxxxxxxxxx xxxxxxxxxxxx -04i/p456 xxxxxxxxxxxxxxxxxxxx yywwnnn
pic16c5x ds30453e-page 172 preliminary ? 1997-2013 microchip technology inc. package marking information (cont?d) xxxxxxxx xxxxxxxx yywwnnn 18-lead cerdip windowed 28-lead cerdip windowed 0001cba example example pic16c54c /jw xxxxxxxxxxx yywwnnn xxxxxxxxxxx pic16c57c /jw 0038cba xxxxxxxxxxx legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 1997-2013 microchip technology inc. preliminary ds30453e-page 173 pic16c5x 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb ? e ? p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c5x ds30453e-page 174 preliminary ? 1997-2013 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb ? e ? p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1997-2013 microchip technology inc. preliminary ds30453e-page 175 pic16c5x 28-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 37.21 36.32 35.43 1.465 1.430 1.395 d overall length 14.22 13.84 12.83 .560 .545 .505 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c ? eb e ? p l a2 b a1 a b1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-079 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c5x ds30453e-page 176 preliminary ? 1997-2013 microchip technology inc. 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l ? c ? h 45 ? 1 2 d p n b e1 e ? a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1997-2013 microchip technology inc. preliminary ds30453e-page 177 pic16c5x 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? 45 ? h ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c5x ds30453e-page 178 preliminary ? 1997-2013 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? ? ? a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1997-2013 microchip technology inc. preliminary ds30453e-page 179 pic16c5x 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l ? c ? ? a2 a1 a ? significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c5x ds30453e-page 180 preliminary ? 1997-2013 microchip technology inc. 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1997-2013 microchip technology inc. preliminary ds30453e-page 181 pic16c5x 28-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 7.37 7.11 6.86 .290 .280 .270 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 37.85 37.08 36.32 1.490 1.460 1.430 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 0.95 0.38 .060 .038 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.72 5.33 4.95 .225 .210 .195 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 w c e eb p a2 l b1 b a1 a * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-013 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c5x ds30453e-page 182 preliminary ? 1997-2013 microchip technology inc. appendix a: compatibility to convert code written for pic16cxx to pic16c5x, the user should take the following steps: 1. check any call , goto or instructions that modify the pc to determine if any program memory page select operations (pa2, pa1, pa0 bits) need to be made. 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any special function register page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to proper value for processor used. 6. remove any use of the addlw, return and sublw instructions. 7. rewrite any code segments that use interrupts. appendix b: revision history revision ke (january 2013) added a note to each package outline drawing.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 183 pic16c5x index a absolute maximum ratings pic16c54/55/56/57 .................................................... 67 pic16c54a ............................................................... 103 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b ............................................................ 131 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b-40 ....................................................... 155 pic16cr54a .............................................................. 79 addwf ............................................................................... 51 alu ....................................................................................... 9 andlw ............................................................................... 51 andwf ............................................................................... 51 applications........................................................................... 5 architectural overview .......................................................... 9 assembler mpasm assembler ..................................................... 61 b block diagram on-chip reset circuit ................................................. 20 pic16c5x series........................................................ 10 timer0 ......................................................................... 37 tmr0/wdt prescaler................................................. 41 watchdog timer .......................................................... 46 brown-out protection circuit .............................................. 23 bsf ..................................................................................... 52 btfsc ................................................................................ 52 btfss ................................................................................ 52 c call ............................................................................. 31, 53 carry (c) bit .................................................................... 9, 29 clocking scheme ................................................................ 13 clrf................................................................................... 53 clrw ................................................................................. 53 clrwdt............................................................................. 53 cmos technology................................................................ 1 code protection ............................................................ 43, 47 comf ................................................................................. 54 compatibility ..................................................................... 182 configuration bits................................................................ 44 d data memory organization ................................................. 26 dc characteristics pic16c54/55/56/57 commercial................................................... 68, 71 extended....................................................... 70, 72 industrial ....................................................... 69, 71 pic16c54a commercial............................................... 104, 109 extended................................................... 106, 109 industrial ................................................... 104, 109 pic16c54c/c55a/c56a/c57c/c58b-40 commercial............................................... 157, 158 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b commercial............................................... 134, 138 extended................................................... 137, 138 industrial ................................................... 134, 138 pic16cr54a commercial................................................... 80, 83 extended ...................................................... 82, 84 industrial ....................................................... 80, 83 pic16lv54a commercial .............................................. 108, 109 industrial ................................................... 108, 109 decf .................................................................................. 54 decfsz ............................................................................. 54 development support ......................................................... 61 device characterization pic16c54/55/56/57/cr54a ....................................... 91 pic16c54a............................................................... 117 pic16c54c/c55a/c56a/c57c/c58b-40 ................. 165 device reset timer (drt) ................................................. 23 device varieties.................................................................... 7 digit carry (dc) bit ......................................................... 9, 29 drt .................................................................................... 23 e electrical specifications pic16c54/55/56/57 .................................................... 67 pic16c54a............................................................... 103 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b ............................................................ 131 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b-40....................................................... 155 pic16cr54a .............................................................. 79 errata .................................................................................... 3 external power-on reset circuit........................................ 21 f family of devices pic16c5x..................................................................... 6 fsr register ...................................................................... 33 value on reset............................................................. 20 g general purpose registers value on reset............................................................. 20 goto ........................................................................... 31, 55 h high-performance risc cpu .............................................. 1 i i/o interfacing ..................................................................... 35 i/o ports ............................................................................. 35 i/o programming considerations ....................................... 36 icepic in-circuit emulator ................................................. 62 id locations.................................................................. 43, 47 incf ................................................................................... 55 incfsz............................................................................... 55 indf register ..................................................................... 33 value on reset............................................................. 20 indirect data addressing .................................................... 33 instruction cycle ................................................................. 13 instruction flow/pipelining .................................................. 13 instruction set summary .................................................... 49 iorlw ................................................................................ 56 iorwf................................................................................ 56 k keeloq evaluation and programming tools ...................... 64 l loading of pc ..................................................................... 31
pic16c5x ds30453e-page 184 preliminary ? 1997-2013 microchip technology inc. m mclr reset register values on ...................................................... 20 memory map pic16c54/cr54/c55.................................................. 25 pic16c56/cr56 ......................................................... 25 pic16c57/cr57/c58/cr58 ....................................... 25 memory organization.......................................................... 25 movf.................................................................................. 56 movlw............................................................................... 56 movwf .............................................................................. 57 mplab c17 and mplab c18 c compilers........................ 61 mplab icd in-circuit debugger......................................... 63 mplab ice high performance universal in-circuit emulator with mplab ide.................................................................. 62 mplab integrated development environment software .... 61 mplink object linker/mplib object librarian .................. 62 n nop .................................................................................... 57 o one-time-programmable (otp) devices............................. 7 option .............................................................................. 57 option register ................................................................ 30 value on reset ............................................................. 20 oscillator configurations ..................................................... 15 oscillator types hs ............................................................................... 15 lp................................................................................ 15 rc ............................................................................... 15 xt ............................................................................... 15 p pa0 bit................................................................................. 29 pa1 bit................................................................................. 29 paging ................................................................................. 31 pc ....................................................................................... 31 value on reset ............................................................. 20 pd bit ............................................................................ 19, 29 peripheral features............................................................... 1 picdem 1 low cost pic mcu demonstration board ........ 63 picdem 17 demonstration board ...................................... 64 picdem 2 low cost pic16cxx demonstration board...... 63 picdem 3 low cost pic16cxxx demonstration board ... 64 picstart plus entry level development programmer .... 63 pin configurations................................................................. 2 pinout description - pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58, pic16cr58 ................................. 11 pinout description - pic16c55, pic16c57, pic16cr57 ... 12 porta................................................................................ 35 value on reset ............................................................. 20 portb................................................................................ 35 value on reset ............................................................. 20 portc................................................................................ 35 value on reset ............................................................. 20 power-down mode.............................................................. 47 power-on reset (por) ...................................................... 21 register values on ...................................................... 20 prescaler ............................................................................. 40 pro mate ii universal device programmer ..................... 63 program counter................................................................. 31 program memory organization ........................................... 25 program verification/code protection................................. 47 q q cycles .............................................................................. 13 quick-turnaround-production (qtp) devices...................... 7 r rc oscillator....................................................................... 17 read only memory (rom) devices ..................................... 7 read-modify-write.............................................................. 36 register file map pic16c54, pic16cr54, pic16c55, pic16c56, pic16cr56 ................................................................ 26 pic16c57/cr57 ......................................................... 27 pic16c58/cr58 ......................................................... 27 registers special function ......................................................... 28 value on reset............................................................. 20 reset .................................................................................. 19 reset on brown-out ........................................................... 23 retlw ............................................................................... 57 rlf ..................................................................................... 58 rrf .................................................................................... 58 s serialized quick-turnaround-production (sqtp) devices... 7 sleep .................................................................... 43, 47, 58 software simulator (mplab sim) ...................................... 62 special features of the cpu .............................................. 43 special function registers ................................................. 28 stack................................................................................... 32 status register ........................................................... 9, 29 value on reset............................................................. 20 subwf............................................................................... 59 swapf ............................................................................... 59 t timer0 switching prescaler assignment ................................ 40 timer0 (tmr0) module............................................... 37 tmr0 register - value on reset................................... 20 tmr0 with external clock .......................................... 39 timing diagrams and specifications pic16c54/55/56/57 .................................................... 74 pic16c54a............................................................... 111 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b ............................................................ 140 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b-40 ....................................................... 160 pic16cr54a .............................................................. 86 timing parameter symbology and load conditions pic16c54/55/56/57 .................................................... 73 pic16c54a............................................................... 110 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b ............................................................ 139 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/ c58b/cr58b-40 ....................................................... 159 pic16cr54a .............................................................. 85 to bit ............................................................................ 19, 29 tris.................................................................................... 59 tris registers ................................................................... 35 value on reset............................................................. 20 u uv erasable devices............................................................ 7
? 1997-2013 microchip technology inc. preliminary ds30453e-page 185 pic16c5x w w register value on reset ............................................................. 20 wake-up from sleep ................................................... 19, 47 watchdog timer (wdt) ................................................ 43, 46 period.......................................................................... 46 programming considerations ..................................... 46 register values on reset ............................................. 20 www, on-line support ....................................................... 3 x xorlw ............................................................................... 60 xorwf............................................................................... 60 z zero (z) bit ...................................................................... 9, 29
pic16c5x ds30453e-page 186 preliminary ? 1997-2013 microchip technology inc. notes:
? 1997-2013 microchip technology inc. preliminary ds30453e-page187 pic16c5x on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events
pic16c5x ds30453e-page188 preliminary ? 1997-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30453e pic16c5x
? 1997-2013 microchip technology inc. preliminary ds30453e-page189 pic16c5x product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. sales and support part no. x /xx xxx pattern package temperature range device device pic16c54 pic16c54t (2) pic16c54a pic16c54at (2) pic16cr54a pic16cr54at (2) pic16c54c pic16c54ct (2) pic16cr54c pic16cr54ct (2) pic16c55 pic16c55t (2) pic16c55a pic16c55at (2) pic16c56 pic16c56t (2) pic16c56a pic16c56at (2) pic16cr56a pic16cr56at (2) pic16c57 pic16c57t (2) pic16c57c pic16c57ct (2) pic16cr57c pic16cr57ct (2) pic16c58b pic16c58bt (2) pic16cr58b pic16cr58bt (2) frequency range/ oscillator type rc resistor capacitor lp low power crystal xt standard crystal/resonator hs high speed crystal 02 200 khz (lp) or 2 mhz (xt and rc) 04 200 khz (lp) or 4 mhz (xt and rc) 10 10 mhz (hs only) 20 20 mhz (hs only) 40 40 mhz (hs only) b (4) no oscillator type for jw packages (3) *rc/lp/xt/hs are for 16c54/55/56/57 devices only -02 is available for 16lv54a only -04/10/20 options are available for all other devices -40 is available for 16c54c/55a/56a/57c/58b devices only temperature range b (4) =0 ? c to +70 ? c i=-40 ? c to +85 ? c e=-40 ? c to +125 ? c package s = die in waffle pack jw = 28-pin 600 mil/18-pin 300 mil windowed cer- dip (3) p = 28-pin 600 mil/18-pin 300 mil pdip so = 300 mil soic ss = 209 mil ssop sp = 28-pin 300 mil skinny pdip *see section 21 for additional package information. pattern qtp, sqtp, rom code (factory specified) or special requirements. blank for otp and windowed devices. examples: a) pic16c55a - 04/p 301 = commercial temp., pdip package, 4 mhz, standard v dd limits, qtp pattern #301 b) pic16lc54c - 04i/so industrial temp., soic package, 200 khz, extended v dd limits c) pic16c57 - rc/sp = rc oscillator, commer- cial temp, skinny pdip package, 4 mhz, stan- dard v dd limits d) pic16c58bt -40/ss 123 = commercial temp, ssop package in tape and reel, 4 mhz, extended v dd limits, rom pattern #123 note 1: c = normal voltage range lc = extended 2: t = in tape and reel - soic and ssop packages only 3: jw devices are uv erasable and can be programmed to any device configura- tion. jw devices meet the electrical requirements of each oscillator type, including lc devices. 4: b = blank x x frequency range/osc type - data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com)
pic16c5x ds30453e-page 190 preliminary ? 1997-2013 microchip technology inc.
? 1997-2013 microchip technology inc. preliminary ds30453e-page 191 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1997-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769355 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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